Added tests for AXI-Lite master

test/peripherals/test_axi_lite.py

@@ -0,0 +1,152 @@
+from coreblocks.peripherals.axi_lite import *
+
+from transactron.lib import AdapterTrans
+
+from ..common import *
+
+
+class AXILiteInterfaceWrapper:
+    def __init__(self, axi_lite_master: Record):
+        self.axi_lite = axi_lite_master
+
+    def slave_ra_ready(self, rdy=1):
+        yield self.axi_lite.read_address.rdy.eq(rdy)
+
+    def slave_ra_wait(self):
+        while not (yield self.axi_lite.read_address.val):
+            yield
+
+    def slave_ra_verify(self, exp_addr, prot):
+        assert (yield self.axi_lite.read_address.val)
+        assert (yield self.axi_lite.read_address.addr) == exp_addr
+        assert (yield self.axi_lite.read_address.prot) == prot
+
+    def slave_rd_wait(self):
+        while not (yield self.axi_lite.read_data.rdy):
+            yield
+
+    def slave_rd_respond(self, data, resp=0):
+        assert (yield self.axi_lite.read_data.rdy)
+        yield self.axi_lite.read_data.data.eq(data)
+        yield self.axi_lite.read_data.resp.eq(resp)
+        yield self.axi_lite.read_data.val.eq(1)
+        yield
+        yield self.axi_lite.read_data.val.eq(0)
+
+    def slave_wa_ready(self, rdy=1):
+        yield self.axi_lite.write_address.rdy.eq(rdy)
+
+    def slave_wa_wait(self):
+        while not (yield self.axi_lite.write_address.val):
+            yield
+
+    def slave_wa_verify(self, exp_addr, prot):
+        assert (yield self.axi_lite.write_address.val)
+        assert (yield self.axi_lite.write_address.addr) == exp_addr
+        assert (yield self.axi_lite.write_address.prot) == prot
+
+    def slave_wd_ready(self, rdy=1):
+        yield self.axi_lite.write_data.rdy.eq(rdy)
+
+    def slave_wd_wait(self):
+        while not (yield self.axi_lite.write_data.val):
+            yield
+
+    def slave_wd_verify(self, exp_data, strb):
+        assert (yield self.axi_lite.write_data.val)
+        assert (yield self.axi_lite.write_data.data) == exp_data
+        assert (yield self.axi_lite.write_data.strb) == strb
+
+    def slave_wr_wait(self):
+        while not (yield self.axi_lite.write_response.rdy):
+            yield
+
+    def slave_wr_respond(self, resp=0):
+        assert (yield self.axi_lite.write_response.rdy)
+        yield self.axi_lite.write_response.resp.eq(resp)
+        yield self.axi_lite.write_response.val.eq(1)
+        yield
+        yield self.axi_lite.write_response.val.eq(0)
+
+
+class TestAXILiteMaster(TestCaseWithSimulator):
+    class AXILiteMasterTestModule(Elaboratable):
+        def __init__(self):
+            pass
+
+        def elaborate(self, platform):
+            m = Module()
+            m.submodules.alm = alm = self.axi_lite_master = AXILiteMaster(AXILiteParameters())
+            m.submodules.rar = self.read_address_request_adapter = TestbenchIO(AdapterTrans(alm.ra_request))
+            m.submodules.rdr = self.read_data_response_adapter = TestbenchIO(AdapterTrans(alm.rd_response))
+            m.submodules.war = self.write_address_request_adapter = TestbenchIO(AdapterTrans(alm.wa_request))
+            m.submodules.wdr = self.write_data_request_adapter = TestbenchIO(AdapterTrans(alm.wd_request))
+            m.submodules.wrr = self.write_response_response_adapter = TestbenchIO(AdapterTrans(alm.wr_response))
+
+            return m
+
+    def test_manual(self):
+        almt = TestAXILiteMaster.AXILiteMasterTestModule()
+
+        def master_process():
+            # read request
+            yield from almt.read_address_request_adapter.call(addr=5, prot=0)
+
+            yield
+
+            yield from almt.read_address_request_adapter.call(addr=10, prot=1)
+
+            yield
+
+            yield from almt.write_address_request_adapter.call(addr=6, prot=0)
+
+            yield
+
+            yield from almt.write_data_request_adapter.call(data=10, strb=3)
+
+        def slave_process():
+            slave = AXILiteInterfaceWrapper(almt.axi_lite_master.axil_master)
+
+            yield from slave.slave_ra_wait()
+            yield from slave.slave_ra_ready(1)
+            yield from slave.slave_ra_verify(5, 0)
+            yield
+            yield Settle()
+
+            yield from slave.slave_ra_wait()
+            yield from slave.slave_rd_wait()
+            yield from slave.slave_ra_ready(1)
+            yield from slave.slave_ra_verify(10, 1)
+            yield from slave.slave_rd_respond(10, 0)
+            yield Settle()
+
+            yield from slave.slave_rd_wait()
+            yield from slave.slave_wa_wait()
+            yield from slave.slave_wd_wait()
+            yield from slave.slave_wa_ready(1)
+            yield from slave.slave_wa_verify(6, 0)
+            yield from slave.slave_wa_ready(1)
+            yield from slave.slave_wd_verify(10, 3)
+            yield from slave.slave_rd_respond(15, 0)
+            yield Settle()
+
+            yield from slave.slave_wr_wait()
+            yield from slave.slave_wr_respond(1)
+            yield Settle()
+
+        def result_process():
+            resp = yield from almt.read_data_response_adapter.call()
+            self.assertEqual(resp["data"], 10)
+            self.assertEqual(resp["resp"], 0)
+
+            resp = yield from almt.read_data_response_adapter.call()
+            self.assertEqual(resp["data"], 15)
+            self.assertEqual(resp["resp"], 0)
+
+            resp = yield from almt.write_response_response_adapter.call()
+            self.assertEqual(resp["resp"], 1)
+
+        with self.run_simulation(almt) as sim:
+            sim.add_sync_process(master_process)
+            sim.add_sync_process(slave_process)
+            sim.add_sync_process(result_process)