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Make RS feed FUs with garbage if flushing
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See #598
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Arusekk committed Oct 29, 2024
1 parent c3edca0 commit 0fb0c82
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Showing 2 changed files with 16 additions and 5 deletions.
17 changes: 12 additions & 5 deletions coreblocks/func_blocks/fu/common/rs.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,9 @@
from coreblocks.params import GenParams
from coreblocks.arch import OpType
from coreblocks.interface.layouts import RSLayouts
from coreblocks.interface.keys import InstructionPrecommitKey
from transactron.lib.metrics import HwExpHistogram, TaggedLatencyMeasurer
from transactron.utils import RecordDict
from transactron.utils import DependencyContext, RecordDict
from transactron.utils import assign
from transactron.utils.assign import AssignType
from transactron.utils.amaranth_ext.functions import popcount
Expand Down Expand Up @@ -44,6 +45,8 @@ def __init__(
self.ready_for = [list(op_list) for op_list in ready_for]
self.get_ready_list = [Method(o=self.layouts.get_ready_list_out, nonexclusive=True) for _ in self.ready_for]

self.dependency_manager = DependencyContext.get()

self.data = Array(Signal(self.internal_layout) for _ in range(self.rs_entries))
self.data_ready = Signal(self.rs_entries)

Expand All @@ -67,10 +70,14 @@ def elaborate(self, platform) -> TModule:
def _elaborate(self, m: TModule, selected_id: Value, select_possible: Value, take_vector: Value):
m.submodules += [self.perf_rs_wait_time, self.perf_num_full]

for i, record in enumerate(self.data):
m.d.comb += self.data_ready[i].eq(
~record.rs_data.rp_s1.bool() & ~record.rs_data.rp_s2.bool() & record.rec_full.bool()
)
with Transaction(name="readiness").body(m):
precommit = self.dependency_manager.get_dependency(InstructionPrecommitKey())
info = precommit(m)
for i, record in enumerate(self.data):
m.d.comb += self.data_ready[i].eq(
(~record.rs_data.rp_s1.bool() & ~record.rs_data.rp_s2.bool() & record.rec_full.bool())
| ~info.side_fx
)

ready_lists: list[Value] = []
for op_list in self.ready_for:
Expand Down
4 changes: 4 additions & 0 deletions transactron/core/tmodule.py
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,10 @@ def __iadd__(self, assigns: StatementLike) -> Self:

class _AvoidingModuleBuilderDomains:
_m: "TModule"
comb: _AvoidingModuleBuilderDomain
av_comb: _AvoidingModuleBuilderDomain
top_comb: _AvoidingModuleBuilderDomain
sync: _AvoidingModuleBuilderDomain

def __init__(self, m: "TModule"):
object.__setattr__(self, "_m", m)
Expand Down

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