Merge branch 'master' into lekcyjna/add-common-now

coreblocks/core.py

@@ -20,7 +20,7 @@
 from coreblocks.frontend.icache import ICache, SimpleWBCacheRefiller, ICacheBypass
 from coreblocks.peripherals.wishbone import WishboneMaster, WishboneBus
 from coreblocks.frontend.fetch import Fetch, UnalignedFetch
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.fifo import BasicFifo
 
 __all__ = ["Core"]
 

coreblocks/frontend/fetch.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from coreblocks.utils.fifo import BasicFifo, Semaphore
+from transactron.utils.fifo import BasicFifo, Semaphore
 from coreblocks.frontend.icache import ICacheInterface
 from coreblocks.frontend.rvc import InstrDecompress, is_instr_compressed
 from transactron import def_method, Method, Transaction, TModule

coreblocks/frontend/icache.py

@@ -8,8 +8,8 @@
 from transactron.core import def_method, Priority, TModule
 from transactron import Method, Transaction
 from coreblocks.params import ICacheLayouts, ICacheParameters
-from coreblocks.utils import assign, OneHotSwitchDynamic
-from coreblocks.utils._typing import HasElaborate
+from transactron.utils import assign, OneHotSwitchDynamic
+from transactron.utils._typing import HasElaborate
 from transactron.lib import *
 from coreblocks.peripherals.wishbone import WishboneMaster
 
@@ -382,30 +382,43 @@ def elaborate(self, platform):
         refill_active = Signal()
         word_counter = Signal(range(self.params.words_in_block))
 
-        with Transaction().body(m, request=refill_active):
+        m.submodules.address_fwd = address_fwd = Forwarder(
+            [("word_counter", word_counter.shape()), ("refill_address", refill_address.shape())]
+        )
+
+        with Transaction().body(m):
+            address = address_fwd.read(m)
             self.wb_master.request(
                 m,
-                addr=Cat(word_counter, refill_address),
+                addr=Cat(address["word_counter"], address["refill_address"]),
                 data=0,
                 we=0,
                 sel=Repl(1, self.wb_master.wb_params.data_width // self.wb_master.wb_params.granularity),
             )
 
         @def_method(m, self.start_refill, ready=~refill_active)
         def _(addr) -> None:
-            m.d.sync += refill_address.eq(addr[self.params.offset_bits :])
+            address = addr[self.params.offset_bits :]
+            m.d.sync += refill_address.eq(address)
             m.d.sync += refill_active.eq(1)
             m.d.sync += word_counter.eq(0)
 
+            address_fwd.write(m, word_counter=0, refill_address=address)
+
         @def_method(m, self.accept_refill, ready=refill_active)
         def _():
             fetched = self.wb_master.result(m)
 
             last = (word_counter == (self.params.words_in_block - 1)) | fetched.err
 
-            m.d.sync += word_counter.eq(word_counter + 1)
+            next_word_counter = Signal.like(word_counter)
+            m.d.top_comb += next_word_counter.eq(word_counter + 1)
+
+            m.d.sync += word_counter.eq(next_word_counter)
             with m.If(last):
                 m.d.sync += refill_active.eq(0)
+            with m.Else():
+                address_fwd.write(m, word_counter=next_word_counter, refill_address=refill_address)
 
             return {
                 "addr": Cat(Repl(0, log2_int(self.params.word_width_bytes)), word_counter, refill_address),

coreblocks/frontend/rvc.py

@@ -2,7 +2,7 @@
 
 from transactron import TModule
 from coreblocks.params import *
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 
 
 # An instruction or an instruction with the valid signal

coreblocks/fu/alu.py

@@ -5,14 +5,14 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import HasElaborate, OneHotSwitch
+from transactron.utils import HasElaborate, OneHotSwitch
 
 from coreblocks.fu.fu_decoder import DecoderManager
 from enum import IntFlag, auto
 
 from coreblocks.utils.protocols import FuncUnit
 
-from coreblocks.utils.utils import popcount, count_leading_zeros
+from transactron.utils.utils import popcount, count_leading_zeros
 
 __all__ = ["AluFuncUnit", "ALUComponent"]
 

coreblocks/fu/div_unit.py

@@ -12,8 +12,8 @@
 
 from coreblocks.fu.fu_decoder import DecoderManager
 
-from coreblocks.utils import OneHotSwitch
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils import OneHotSwitch
+from transactron.utils.fifo import BasicFifo
 from coreblocks.utils.protocols import FuncUnit
 from coreblocks.fu.division.long_division import LongDivider
 

coreblocks/fu/exception.py

@@ -7,7 +7,7 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.params.keys import ExceptionReportKey
 
 from coreblocks.fu.fu_decoder import DecoderManager

coreblocks/fu/jumpbranch.py

@@ -9,7 +9,7 @@
 from transactron.lib import *
 
 from coreblocks.params import *
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 from coreblocks.fu.fu_decoder import DecoderManager

coreblocks/fu/mul_unit.py

@@ -18,7 +18,7 @@
 
 __all__ = ["MulUnit", "MulFn", "MulComponent", "MulType"]
 
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 

coreblocks/fu/shift_unit.py

@@ -5,7 +5,7 @@
 from transactron.lib import FIFO
 
 from coreblocks.params import OpType, Funct3, Funct7, GenParams, FuncUnitLayouts, FunctionalComponentParams
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 
 from coreblocks.fu.fu_decoder import DecoderManager
 from enum import IntFlag, auto

coreblocks/fu/zbc.py

@@ -14,7 +14,7 @@
 )
 from transactron import Method, def_method, TModule
 from transactron.lib import FIFO
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 

coreblocks/fu/zbs.py

@@ -5,7 +5,7 @@
 from coreblocks.params import Funct3, GenParams, FuncUnitLayouts, OpType, Funct7, FunctionalComponentParams
 from transactron import Method, TModule, def_method
 from transactron.lib import FIFO
-from coreblocks.utils import OneHotSwitch
+from transactron.utils import OneHotSwitch
 from coreblocks.utils.protocols import FuncUnit
 
 from coreblocks.fu.fu_decoder import DecoderManager

coreblocks/lsu/dummyLsu.py

@@ -3,7 +3,7 @@
 from transactron import Method, def_method, Transaction, TModule
 from coreblocks.params import *
 from coreblocks.peripherals.wishbone import WishboneMaster
-from coreblocks.utils import assign, ModuleLike
+from transactron.utils import assign, ModuleLike
 from coreblocks.utils.protocols import FuncBlock
 
 

coreblocks/params/instr.py

@@ -3,7 +3,7 @@
 from amaranth.hdl.ast import ValueCastable
 from amaranth import *
 
-from coreblocks.utils import ValueLike
+from transactron.utils import ValueLike
 from coreblocks.params.isa import *
 
 

coreblocks/params/layouts.py

@@ -1,6 +1,6 @@
 from coreblocks.params import GenParams, OpType, Funct7, Funct3
 from coreblocks.params.isa import ExceptionCause
-from coreblocks.utils.utils import layout_subset
+from transactron.utils.utils import layout_subset
 
 __all__ = [
     "SchedulerLayouts",

coreblocks/peripherals/wishbone.py

@@ -6,9 +6,11 @@
 import operator
 
 from transactron import Method, def_method, TModule
+from transactron.core import Transaction
 from transactron.lib import AdapterTrans
-from coreblocks.utils.utils import OneHotSwitchDynamic, assign
-from coreblocks.utils.fifo import BasicFifo
+from transactron.utils.utils import OneHotSwitchDynamic, assign
+from transactron.utils.fifo import BasicFifo
+from transactron.lib.connectors import Forwarder
 
 
 class WishboneParameters:
@@ -109,8 +111,6 @@ def __init__(self, wb_params: WishboneParameters):
         self.request = Method(i=self.requestLayout)
         self.result = Method(o=self.resultLayout)
 
-        self.ready = Signal()
-        self.res_ready = Signal()
         self.result_data = Record(self.resultLayout)
 
         # latched input signals
@@ -132,6 +132,10 @@ def generate_layouts(self, wb_params: WishboneParameters):
     def elaborate(self, platform):
         m = TModule()
 
+        m.submodules.result = result = Forwarder(self.resultLayout)
+
+        request_ready = Signal()
+
         def FSMWBCycStart(request):  # noqa: N802
             # internal FSM function that starts Wishbone cycle
             m.d.sync += self.wbMaster.cyc.eq(1)
@@ -140,49 +144,54 @@ def FSMWBCycStart(request):  # noqa: N802
             m.d.sync += self.wbMaster.dat_w.eq(Mux(request.we, request.data, 0))
             m.d.sync += self.wbMaster.we.eq(request.we)
             m.d.sync += self.wbMaster.sel.eq(request.sel)
-            m.next = "WBWaitACK"
-
-        @def_method(m, self.result, ready=self.res_ready)
-        def _():
-            m.d.sync += self.res_ready.eq(0)
-            return self.result_data
 
         with m.FSM("Reset"):
             with m.State("Reset"):
                 m.d.sync += self.wbMaster.rst.eq(1)
                 m.next = "Idle"
             with m.State("Idle"):
                 # default values for important signals
-                m.d.sync += self.ready.eq(1)
                 m.d.sync += self.wbMaster.rst.eq(0)
                 m.d.sync += self.wbMaster.stb.eq(0)
                 m.d.sync += self.wbMaster.cyc.eq(0)
-
-                @def_method(m, self.request, ready=(self.ready & ~self.res_ready))
-                def _(arg):
-                    m.d.sync += self.ready.eq(0)
-                    m.d.sync += assign(self.txn_req, arg)
-                    # do WBCycStart state in the same clock cycle
-                    FSMWBCycStart(arg)
+                m.d.comb += request_ready.eq(1)
+                with m.If(self.request.run):
+                    m.next = "WBWaitACK"
 
             with m.State("WBCycStart"):
                 FSMWBCycStart(self.txn_req)
                 m.next = "WBWaitACK"
 
             with m.State("WBWaitACK"):
                 with m.If(self.wbMaster.ack | self.wbMaster.err):
-                    m.d.sync += self.wbMaster.cyc.eq(0)
-                    m.d.sync += self.wbMaster.stb.eq(0)
-                    m.d.sync += self.ready.eq(1)
-                    m.d.sync += self.res_ready.eq(1)
-                    m.d.sync += self.result_data.data.eq(Mux(self.txn_req.we, 0, self.wbMaster.dat_r))
-                    m.d.sync += self.result_data.err.eq(self.wbMaster.err)
-                    m.next = "Idle"
+                    m.d.comb += request_ready.eq(result.read.run)
+                    with Transaction().body(m):
+                        # will be always ready, as we checked that in Idle
+                        result.write(m, data=Mux(self.txn_req.we, 0, self.wbMaster.dat_r), err=self.wbMaster.err)
+                    with m.If(self.request.run):
+                        m.next = "WBWaitACK"
+                    with m.Else():
+                        m.d.sync += self.wbMaster.cyc.eq(0)
+                        m.d.sync += self.wbMaster.stb.eq(0)
+                        m.next = "Idle"
                 with m.If(self.wbMaster.rty):
                     m.d.sync += self.wbMaster.cyc.eq(1)
                     m.d.sync += self.wbMaster.stb.eq(0)
                     m.next = "WBCycStart"
 
+        @def_method(m, self.result)
+        def _():
+            return result.read(m)
+
+        @def_method(m, self.request, ready=request_ready & result.write.ready)
+        def _(arg):
+            m.d.sync += assign(self.txn_req, arg)
+            # do WBCycStart state in the same clock cycle
+            FSMWBCycStart(arg)
+
+        result.write.schedule_before(self.request)
+        result.read.schedule_before(self.request)
+
         return m
 
 

coreblocks/scheduler/scheduler.py

@@ -5,7 +5,7 @@
 from transactron import Method, Transaction, TModule
 from transactron.lib import FIFO, Forwarder
 from coreblocks.params import SchedulerLayouts, GenParams, OpType
-from coreblocks.utils import assign, AssignType
+from transactron.utils import assign, AssignType
 from coreblocks.utils.protocols import FuncBlock
 
 

coreblocks/scheduler/wakeup_select.py

@@ -1,7 +1,7 @@
 from amaranth import *
 
 from coreblocks.params import GenParams, FuncUnitLayouts
-from coreblocks.utils import assign, AssignType
+from transactron.utils import assign, AssignType
 from transactron.core import *
 
 __all__ = ["WakeupSelect"]

coreblocks/structs_common/csr.py

@@ -3,7 +3,7 @@
 from dataclasses import dataclass
 
 from transactron import Method, def_method, Transaction, TModule
-from coreblocks.utils import assign, bits_from_int
+from transactron.utils import assign, bits_from_int
 from coreblocks.params.genparams import GenParams
 from coreblocks.params.dependencies import DependencyManager, ListKey
 from coreblocks.params.fu_params import BlockComponentParams

coreblocks/utils/__init__.py

@@ -1,3 +0,0 @@
-from .utils import *  # noqa: F401
-from ._typing import *  # noqa: F401
-from .debug_signals import *  # noqa: F401

coreblocks/utils/protocols.py

@@ -1,6 +1,6 @@
 from typing import Protocol
 from transactron import Method
-from ._typing import HasElaborate
+from transactron.utils._typing import HasElaborate
 
 
 __all__ = ["FuncUnit", "FuncBlock", "Unifier"]

scripts/gen_verilog.py

@@ -16,7 +16,7 @@
 from coreblocks.peripherals.wishbone import WishboneBus
 from coreblocks.core import Core
 from transactron import TransactionModule
-from coreblocks.utils.utils import flatten_signals
+from transactron.utils.utils import flatten_signals
 
 from coreblocks.params.configurations import *
 

scripts/synthesize.py

@@ -13,7 +13,7 @@
     sys.path.insert(0, parent)
 
 
-from coreblocks.utils.utils import ModuleConnector
+from transactron.utils.utils import ModuleConnector
 from coreblocks.params.genparams import GenParams
 from coreblocks.params.fu_params import FunctionalComponentParams
 from coreblocks.core import Core

test/common/functions.py

@@ -2,7 +2,8 @@
 from amaranth.hdl.ast import Statement
 from amaranth.sim.core import Command
 from typing import TypeVar, Any, Generator, TypeAlias, TYPE_CHECKING, Union
-from coreblocks.utils._typing import RecordValueDict, RecordIntDict
+from transactron.utils._typing import RecordValueDict, RecordIntDict
+
 
 if TYPE_CHECKING:
     from .infrastructure import CoreblocksCommand

test/common/infrastructure.py

@@ -13,7 +13,7 @@
 from transactron import Method
 from transactron.lib import AdapterTrans
 from transactron.core import TransactionModule
-from coreblocks.utils import ModuleConnector, HasElaborate, auto_debug_signals, HasDebugSignals
+from transactron.utils import ModuleConnector, HasElaborate, auto_debug_signals, HasDebugSignals
 
 T = TypeVar("T")
 _T_nested_collection: TypeAlias = T | list["_T_nested_collection[T]"] | dict[str, "_T_nested_collection[T]"]

test/common/sugar.py

@@ -1,7 +1,7 @@
 import functools
 from typing import Callable, Any, Optional
 from .testbenchio import TestbenchIO, TestGen
-from coreblocks.utils._typing import RecordIntDict
+from transactron.utils._typing import RecordIntDict
 
 
 def def_method_mock(

test/common/testbenchio.py

@@ -4,7 +4,7 @@
 from transactron.lib import AdapterBase
 from transactron.core import ValueLike, SignalBundle
 from transactron._utils import mock_def_helper
-from coreblocks.utils._typing import RecordIntDictRet, RecordValueDict, RecordIntDict
+from transactron.utils._typing import RecordIntDictRet, RecordValueDict, RecordIntDict
 from .functions import set_inputs, get_outputs, TestGen