Add TaggedCounter #2564
xThaidmain.yml
on: pull_request
Synthesize full core
31s
Build regression tests (riscv-tests)
2m 59s
Build regression tests (riscv-arch-test)
41s
Run unit tests
6m 10s
Check code formatting and typing
32s
Run regression tests (riscv-tests)
3m 56s
Run regression tests (riscv-arch-test)
11m 52s
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
verilog-full-core
Expired
|
327 KB |
|