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Add TaggedCounter #2563

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Add TaggedCounter

Add TaggedCounter #2563

Triggered via pull request March 31, 2024 16:59
@xThaidxThaid
opened #637
xThaid:tagged_counter
Status Failure
Total duration 12m 44s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
29s
Synthesize full core
Build regression tests (riscv-tests)
38s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
46s
Build regression tests (riscv-arch-test)
Run unit tests
6m 24s
Run unit tests
Check code formatting and typing
38s
Check code formatting and typing
Run regression tests (riscv-tests)
4m 10s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
11m 41s
Run regression tests (riscv-arch-test)
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1 error
Check code formatting and typing
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
verilog-full-core Expired
327 KB