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Allow parallel compilation of the verilated model #2521

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Allow parallel compilation of the verilated model

Allow parallel compilation of the verilated model #2521

Triggered via pull request March 21, 2024 21:57
@tilktilk
synchronize #623
tilk/parallel-verilator-compilation
Status Success
Total duration 14m 54s
Artifacts 3

main.yml

on: pull_request
Synthesize full core
31s
Synthesize full core
Build regression tests (riscv-tests)
1m 23s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
3m 5s
Build regression tests (riscv-arch-test)
Run unit tests
6m 34s
Run unit tests
Check code formatting and typing
48s
Check code formatting and typing
Run regression tests (riscv-tests)
4m 4s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
11m 34s
Run regression tests (riscv-arch-test)
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Artifacts

Produced during runtime
Name Size
artifact Expired
643 KB
riscof-tests Expired
746 KB
verilog-full-core Expired
323 KB