Far path for fpu adder/subtractor #3113
main.yml
on: pull_request
Synthesize full core
41s
Build regression tests (riscv-tests)
51s
Build regression tests (riscv-arch-test)
44s
Run unit tests
6m 54s
Check code formatting and typing
32s
Run regression tests (riscv-tests)
4m 35s
Run regression tests (riscv-arch-test)
14m 2s
Annotations
7 warnings
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
verilog-full-core
|
542 KB |
|