CI

mtvec vectored mode (#755) #3103

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Triggered via push November 26, 2024 13:50

tilk

master

Status Success

Total duration 17m 0s

Artifacts 1

main.yml

on: push

Synthesize full core

Build regression tests (riscv-tests)

Build regression tests (riscv-arch-test)

Check code formatting and typing

Run regression tests (riscv-tests)

Run regression tests (riscv-arch-test)

Artifacts

Produced during runtime

Name	Size
verilog-full-core	544 KB