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Fix synthesis of some configurations #3047

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Fix synthesis of some configurations

Fix synthesis of some configurations #3047

Triggered via pull request November 12, 2024 19:27
@tilktilk
synchronize #750
piotro888:piotro/fix-no-icache
Status Success
Total duration 16m 23s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
34s
Synthesize full core
Build regression tests (riscv-tests)
39s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
43s
Build regression tests (riscv-arch-test)
Run unit tests
7m 55s
Run unit tests
Check code formatting and typing
40s
Check code formatting and typing
Run regression tests (riscv-tests)
5m 47s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
15m 16s
Run regression tests (riscv-arch-test)
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Artifacts

Produced during runtime
Name Size
verilog-full-core
539 KB