FPU rounding module #3042
tilkmain.yml
on: pull_request
Synthesize full core
33s
Build regression tests (riscv-tests)
37s
Build regression tests (riscv-arch-test)
38s
Run unit tests
7m 43s
Check code formatting and typing
42s
Run regression tests (riscv-tests)
5m 23s
Run regression tests (riscv-arch-test)
14m 47s
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
verilog-full-core
|
539 KB |
|