Merge branch 'master' of https://github.com/kelvinlawson/atomthreads

kernel/atom.h

@@ -42,15 +42,6 @@ extern "C" {
 /* Forward declaration */
 struct atom_tcb;
 
-/*
- * Define THREAD_PORT_PRIV to be empty if the used atomport.h does not define
- * a port specific entry for the atom_tcb struct. This way we do not have an
- * unused element.
- */ 
-#if !defined(THREAD_PORT_PRIV)
-#define THREAD_PORT_PRIV
-#endif
-
 typedef struct atom_tcb
 {
  /*
@@ -60,7 +51,9 @@ typedef struct atom_tcb
  POINTER sp_save_ptr;
 
  /* Thread's port specific private data */
+#if defined(THREAD_PORT_PRIV)
  THREAD_PORT_PRIV;
+#endif
 
  /* Thread priority (0-255) */
  uint8_t priority;

kernel/atomkernel.c

@@ -404,6 +404,7 @@ uint8_t atomThreadCreate (ATOM_TCB *tcb_ptr, uint8_t priority, void (*entry_poin
 
  /* Set up the TCB initial values */
  tcb_ptr->suspended = FALSE;
+ tcb_ptr->terminated = FALSE;
  tcb_ptr->priority = priority;
  tcb_ptr->prev_tcb = NULL;
  tcb_ptr->next_tcb = NULL;

ports/arm/platforms/dm36x/dm36x-io.h

@@ -319,6 +319,7 @@
 #define DM36X_PSC_MDSTAT_BASE 0x800
 #define DM36X_PSC_MDCTL_BASE 0xA00
 #define DM36X_PSC_MOD_SPI1 6
+#define DM36X_PSC_MOD_MCBSP 8
 #define DM36X_PSC_MOD_SPI2 11
 #define DM36X_PSC_MOD_I2C 18
 #define DM36X_PSC_MOD_SPI0 22
@@ -442,6 +443,22 @@
 #define DM36X_INTC_VEC_UART1INT 41
 #define DM36X_INTC_VEC_SPI0INT0 42
 #define DM36X_INTC_VEC_SPI3INT0 43
+#define DM36X_INTC_VEC_GIO0 44
+#define DM36X_INTC_VEC_GIO1 45
+#define DM36X_INTC_VEC_GIO2 46
+#define DM36X_INTC_VEC_GIO3 47
+#define DM36X_INTC_VEC_GIO4 48
+#define DM36X_INTC_VEC_GIO5 49
+#define DM36X_INTC_VEC_GIO6 50
+#define DM36X_INTC_VEC_GIO7 51
+#define DM36X_INTC_VEC_GIO8 52
+#define DM36X_INTC_VEC_GIO9 53
+#define DM36X_INTC_VEC_GIO10 54
+#define DM36X_INTC_VEC_GIO11 55
+#define DM36X_INTC_VEC_GIO12 56
+#define DM36X_INTC_VEC_GIO13 57
+#define DM36X_INTC_VEC_GIO14 58
+#define DM36X_INTC_VEC_GIO15 59
 #define DM36X_INTC_MAX_VEC 63
 
 
@@ -474,27 +491,38 @@
 
 
 /** GPIO registers */
-#define DM36X_GPIO_BASE 0x01C67000
-#define DM36X_GPIO_DIR01 0x10
-#define DM36X_GPIO_OUT01 0x14
-#define DM36X_GPIO_SET01 0x18
-#define DM36X_GPIO_CLR01 0x1C
-#define DM36X_GPIO_IN01 0x20
-#define DM36X_GPIO_DIR23 0x38
-#define DM36X_GPIO_OUT23 0x3C
-#define DM36X_GPIO_SET23 0x40
-#define DM36X_GPIO_CLR23 0x44
-#define DM36X_GPIO_IN23 0x48
-#define DM36X_GPIO_DIR45 0x60
-#define DM36X_GPIO_OUT45 0x64
-#define DM36X_GPIO_SET45 0x68
-#define DM36X_GPIO_CLR45 0x6C
-#define DM36X_GPIO_IN45 0x70
-#define DM36X_GPIO_DIR6 0x88
-#define DM36X_GPIO_OUT6 0x8C
-#define DM36X_GPIO_SET6 0x90
-#define DM36X_GPIO_CLR6 0x94
-#define DM36X_GPIO_IN6 0x98
+#define DM36X_GPIO_BASE 0x01C67000
+#define DM36X_GPIO_BINTEN 0x08
+#define DM36X_GPIO_DIR01 0x10
+#define DM36X_GPIO_OUT01 0x14
+#define DM36X_GPIO_SET01 0x18
+#define DM36X_GPIO_CLR01 0x1C
+#define DM36X_GPIO_IN01 0x20
+#define DM36X_GPIO_SET_RIS_TRIG01 0x24
+#define DM36X_GPIO_CLR_RIS_TRIG01 0x28
+#define DM36X_GPIO_SET_FAL_TRIG01 0x2C
+#define DM36X_GPIO_CLR_FAL_TRIG01 0x30
+#define DM36X_GPIO_INTSTAT01 0x34
+#define DM36X_GPIO_DIR23 0x38
+#define DM36X_GPIO_OUT23 0x3C
+#define DM36X_GPIO_SET23 0x40
+#define DM36X_GPIO_CLR23 0x44
+#define DM36X_GPIO_IN23 0x48
+#define DM36X_GPIO_DIR45 0x60
+#define DM36X_GPIO_OUT45 0x64
+#define DM36X_GPIO_SET45 0x68
+#define DM36X_GPIO_CLR45 0x6C
+#define DM36X_GPIO_IN45 0x70
+#define DM36X_GPIO_DIR6 0x88
+#define DM36X_GPIO_OUT6 0x8C
+#define DM36X_GPIO_SET6 0x90
+#define DM36X_GPIO_CLR6 0x94
+#define DM36X_GPIO_IN6 0x98
+#define DM36X_GPIO_SET_RIS_TRIG6 0x9C
+#define DM36X_GPIO_CLR_RIS_TRIG6 0xA0
+#define DM36X_GPIO_SET_FAL_TRIG6 0xA4
+#define DM36X_GPIO_CLR_FAL_TRIG6 0xA8
+#define DM36X_GPIO_INTSTAT6 0xAC
 
 
 /** VPFE/VPBE registers */
@@ -541,6 +569,26 @@
 #define DM36X_SD_MMCFIFOCTL 0x74
 
 
+/** McBSP registers */
+#define DM36X_MCBSP_BASE 0x01D02000 /* McBSP */
+#define DM36X_MCBSP_DRR 0x00
+#define DM36X_MCBSP_DXR 0x04
+#define DM36X_MCBSP_SPCR 0x08
+#define DM36X_MCBSP_RCR 0x0C
+#define DM36X_MCBSP_XCR 0x10
+#define DM36X_MCBSP_SRGR 0x14
+#define DM36X_MCBSP_MCR 0x18
+#define DM36X_MCBSP_RCERE0 0x1C
+#define DM36X_MCBSP_XCERE0 0x20
+#define DM36X_MCBSP_PCR 0x24
+#define DM36X_MCBSP_RCERE1 0x28
+#define DM36X_MCBSP_XCERE1 0x2C
+#define DM36X_MCBSP_RCERE2 0x30
+#define DM36X_MCBSP_XCERE2 0x34
+#define DM36X_MCBSP_RCERE3 0x38
+#define DM36X_MCBSP_XCERE3 0x3C
+
+
 /* Function prototypes */
 extern int low_level_init (void) ;
 

ports/avr/Makefile

@@ -36,7 +36,7 @@ PART=atmega16
 BUILD_DIR=build
 
 # Port/application object files
-APP_OBJECTS = atomport.o uart.o tests-main.o
+APP_OBJECTS = atomport.o atomport-private.o uart.o tests-main.o
 APP_ASM_OBJECTS = atomport-asm.o
 
 # Kernel object files

ports/avr/atomport-private.c

@@ -0,0 +1,90 @@
+#include <avr/interrupt.h>
+
+#include "atom.h"
+#include "atomport-private.h"
+
+/**
+ * \b avrInitSystemTickTimer
+ *
+ * Initialise the system tick timer. Uses the AVR's timer1 facility.
+ *
+ * @return None
+ */
+void avrInitSystemTickTimer ( void )
+{
+ /* Set timer 1 compare match value for configured system tick,
+ * with a prescaler of 256. We will get a compare match 1A
+ * interrupt on every system tick, in which we must call the
+ * OS's system tick handler. */
+ OCR1A = (AVR_CPU_HZ / 256 / SYSTEM_TICKS_PER_SEC);
+
+ /* Enable compare match 1A interrupt */
+#ifdef TIMSK
+ TIMSK = _BV(OCIE1A);
+#else
+ TIMSK1 = _BV(OCIE1A);
+#endif
+
+ /* Set prescaler 256 */
+ TCCR1B = _BV(CS12) | _BV(WGM12);
+}
+
+
+/**
+ *
+ * System tick ISR.
+ *
+ * This is responsible for regularly calling the OS system tick handler.
+ * The system tick handler checks if any timer callbacks are necessary,
+ * and runs the scheduler.
+ *
+ * The compiler automatically saves all registers necessary before calling
+ * out to a C routine. This will be (at least) R0, R1, SREG, R18-R27 and
+ * R30/R31.
+ *
+ * The system may decide to schedule in a new thread during the call to
+ * atomTimerTick(), in which case around half of the thread's context will
+ * already have been saved here, ready for when we return here when the
+ * interrupted thread is scheduled back in. The remaining context will be
+ * saved by the context switch routine.
+ *
+ * As with all interrupts, the ISR should call atomIntEnter() and
+ * atomIntExit() on entry and exit. This serves two purposes:
+ *
+ * a) To notify the OS that it is running in interrupt context
+ * b) To defer the scheduler until after the ISR is completed
+ *
+ * We defer all scheduling decisions until after the ISR has completed
+ * in case the interrupt handler makes more than one thread ready.
+ *
+ * @return None
+ */
+ISR (TIMER1_COMPA_vect)
+{
+ /* Call the interrupt entry routine */
+ atomIntEnter();
+
+ /* Call the OS system tick handler */
+ atomTimerTick();
+
+ /* Call the interrupt exit routine */
+ atomIntExit(TRUE);
+}
+
+
+/**
+ *
+ * Default (no handler installed) ISR.
+ *
+ * Installs a default handler to be called if any interrupts occur for
+ * which we have not registered an ISR. This is empty and has only been
+ * included to handle user-created code which may enable interrupts. The
+ * core OS does not enable any interrupts other than the system timer
+ * tick interrupt.
+ *
+ * @return None
+ */
+ISR (BADISR_vect)
+{
+ /* Empty */
+}

ports/avr/atomport-private.h

@@ -31,9 +31,21 @@
 #define __ATOM_PORT_PRIVATE_H
 
 /* CPU Frequency */
+#ifdef F_CPU
+#define AVR_CPU_HZ F_CPU
+#else
 #define AVR_CPU_HZ 1000000
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* Function prototypes */
 void avrInitSystemTickTimer ( void );
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ATOM_PORT_PRIVATE_H */

ports/avr/atomport.c

@@ -28,10 +28,7 @@
  */
 
 
-#include <avr/interrupt.h>
-
 #include "atom.h"
-#include "atomport-private.h"
 
 
 /** Forward declarations */
@@ -268,89 +265,3 @@ void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_poi
 
 }
 
-
-/**
- * \b avrInitSystemTickTimer
- *
- * Initialise the system tick timer. Uses the AVR's timer1 facility.
- *
- * @return None
- */
-void avrInitSystemTickTimer ( void )
-{
- /* Set timer 1 compare match value for configured system tick,
- * with a prescaler of 256. We will get a compare match 1A
- * interrupt on every system tick, in which we must call the
- * OS's system tick handler. */
- OCR1A = (AVR_CPU_HZ / 256 / SYSTEM_TICKS_PER_SEC);
-
- /* Enable compare match 1A interrupt */
-#ifdef TIMSK
- TIMSK = _BV(OCIE1A);
-#else
- TIMSK1 = _BV(OCIE1A);
-#endif
-
- /* Set prescaler 256 */
- TCCR1B = _BV(CS12) | _BV(WGM12);
-}
-
-
-/**
- *
- * System tick ISR.
- *
- * This is responsible for regularly calling the OS system tick handler.
- * The system tick handler checks if any timer callbacks are necessary,
- * and runs the scheduler.
- *
- * The compiler automatically saves all registers necessary before calling
- * out to a C routine. This will be (at least) R0, R1, SREG, R18-R27 and
- * R30/R31.
- *
- * The system may decide to schedule in a new thread during the call to
- * atomTimerTick(), in which case around half of the thread's context will
- * already have been saved here, ready for when we return here when the
- * interrupted thread is scheduled back in. The remaining context will be
- * saved by the context switch routine.
- *
- * As with all interrupts, the ISR should call atomIntEnter() and
- * atomIntExit() on entry and exit. This serves two purposes:
- *
- * a) To notify the OS that it is running in interrupt context
- * b) To defer the scheduler until after the ISR is completed
- *
- * We defer all scheduling decisions until after the ISR has completed
- * in case the interrupt handler makes more than one thread ready.
- *
- * @return None
- */
-ISR (TIMER1_COMPA_vect)
-{
- /* Call the interrupt entry routine */
- atomIntEnter();
-
- /* Call the OS system tick handler */
- atomTimerTick();
-
- /* Call the interrupt exit routine */
- atomIntExit(TRUE);
-}
-
-
-/**
- *
- * Default (no handler installed) ISR.
- *
- * Installs a default handler to be called if any interrupts occur for
- * which we have not registered an ISR. This is empty and has only been
- * included to handle user-created code which may enable interrupts. The
- * core OS does not enable any interrupts other than the system timer
- * tick interrupt.
- *
- * @return None
- */
-ISR (BADISR_vect)
-{
- /* Empty */
-}

ports/avr/uart.h

@@ -13,6 +13,9 @@
 
 #include "atom.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /*
  * Perform UART startup initialization.
@@ -23,3 +26,7 @@ int uart_init(uint32_t baudrate);
  * Send one character to the UART.
  */
 int uart_putchar(char c, FILE *stream);
+
+#ifdef __cplusplus
+}
+#endif