HACOGen - hardware compressor generator

Hardware compressor generator (HACOGen), written in Chisel3, is a generator framework for hardware stream compressors. The current version generates a simple zero-skimming compressor logic (Figure below). The compressor receives data as a vector of elements every single cycle, compress the data and stack it into an internal buffer. When the buffer gets full, the flush signal is raised; its content is ready to be read. This reposiroty also includes a Scala-based estimation tool to evaluate different compresison schemes and operations such as runlength, zero skimming and a bit shuffle operation.

Getting Started

 $ git clone https://github.com/kazutomo/hacogen.git
 $ cd hacogen
 $ make test

NOTE: I personally tested hacogen on Fedora28 and Fedora32. Additional packages you need to install are sbt and verilator. I hope this should work on other Linux distros as well.

How to use HACOGen

 $ ./run.sh l         # list available targets
 $ ./run.sh t TARGET  # test the specified module
 $ ./run.sh s TARGET  # simulate the specified module

 NOTE: Replace TARGET with one of the available targets

 You can also use make:

 $ make TARGET       # test using Scala-based simulator
 $ make TARGET.v     # generate Verilog file
 $ make TARGET.vcd   # simulate using Verilator

Design RTL view

Simulation results

simulation result in text file

Component RTL view

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Developed by Kazutomo Yoshii [email protected]