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Added corrections to verilog source and configurations for the openlane
macro hardening and top level synthesis. Removed old files that corresponded to the caravan design and not to the openframe design.
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Original file line number | Diff line number | Diff line change |
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VERSION 5.7 ; | ||
NOWIREEXTENSIONATPIN ON ; | ||
DIVIDERCHAR "/" ; | ||
BUSBITCHARS "[]" ; | ||
MACRO vccd1_connection | ||
CLASS BLOCK ; | ||
FOREIGN vccd1_connection ; | ||
ORIGIN 0.000 0.000 ; | ||
SIZE 45.400 BY 74.600 ; | ||
OBS | ||
LAYER met3 ; | ||
RECT 0.105 0.100 45.340 74.300 ; | ||
END | ||
END vccd1_connection | ||
END LIBRARY | ||
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This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,16 @@ | ||
VERSION 5.7 ; | ||
NOWIREEXTENSIONATPIN ON ; | ||
DIVIDERCHAR "/" ; | ||
BUSBITCHARS "[]" ; | ||
MACRO vssd1_connection | ||
CLASS BLOCK ; | ||
FOREIGN vssd1_connection ; | ||
ORIGIN 0.000 0.000 ; | ||
SIZE 45.400 BY 74.600 ; | ||
OBS | ||
LAYER met3 ; | ||
RECT 0.105 0.100 45.340 74.300 ; | ||
END | ||
END vssd1_connection | ||
END LIBRARY | ||
|
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