Update mesh and transposer skeleton

hazardflow-designs/src/gemmini/execute/systolic_array/mesh.rs

@@ -11,6 +11,31 @@ pub type MeshRowData = [TileRowData; MESH_ROWS];
 /// Mesh column data. It consists of `MESH_COLS` tile column data.
 pub type MeshColData = [TileColData; MESH_COLS];
 
+/// Applies a 1-cycle delay register to the row-side egress interface of a tile.
+///
+/// This helper function is used with the `array_map!` macro, as the macro currently does not accept closures as arguments.
+fn reg_fwd_tile_row(i: Valid<PeRowData>) -> Valid<PeRowData> {
+    todo!("assignment 5")
+}
+
+/// Applies a 1-cycle delay register to the column-side egress interface of a tile.
+///
+/// This helper function is used with the `array_map!` macro, as the macro currently does not accept closures as arguments.
+fn reg_fwd_tile_col((i1, i2): (Valid<PeColData>, Valid<PeColControl>)) -> (Valid<PeColData>, Valid<PeColControl>) {
+    todo!("assignment 5")
+}
+
+/// A tile with a 1-cycle delay register attached to each egress interface.
+///
+/// This is used as a component within the Mesh.
+pub fn tile_with_reg(in_left: TileRowData, in_top: TileColData) -> (TileRowData, TileColData) {
+    let (out_right, out_bottom) = tile(in_left, in_top);
+
+    // NOTE: The `array_map!` macro currently does not accept closures as arguments, so we defined helper functions
+    //       instead of inlining it.
+    (array_map!(out_right, reg_fwd_tile_row), array_map!(out_bottom, reg_fwd_tile_col))
+}
+
 /// Mesh.
 pub fn mesh(in_left: MeshRowData, in_top: MeshColData) -> (MeshRowData, MeshColData) {
     todo!("assignment 5")

hazardflow-designs/src/gemmini/execute/systolic_array/transposer.rs

@@ -4,49 +4,68 @@
 
 use super::*;
 
-#[derive(Debug, Clone, Copy)]
+/// Indicates the direction of the Transposer PE.
+#[derive(Debug, Default, Clone, Copy)]
 enum Dir {
-    Left,
-    Up,
+    /// Selects data from row side.
+    #[default]
+    Row,
+
+    /// Selects data from column side.
+    Col,
 }
 
 impl Dir {
     fn flip(self) -> Self {
         match self {
-            Dir::Left => Dir::Up,
-            Dir::Up => Dir::Left,
+            Dir::Row => Dir::Col,
+            Dir::Col => Dir::Row,
         }
     }
 }
 
-/// Returns `(out_right, (out_bottom, dir))`.
-fn t_pe(
-    in_left: Valid<U<INPUT_BITS>>,
-    (in_top, dir): (Valid<U<INPUT_BITS>>, Valid<Dir>),
-) -> (Valid<U<INPUT_BITS>>, (Valid<U<INPUT_BITS>>, Valid<Dir>)) {
+/// Transposer PE.
+fn transposer_pe(
+    in_row: Valid<S<INPUT_BITS>>,
+    (in_col, in_dir): (Valid<S<INPUT_BITS>>, Valid<Dir>),
+) -> (Valid<S<INPUT_BITS>>, (Valid<S<INPUT_BITS>>, Valid<Dir>)) {
     todo!("assignment 5")
 }
 
-// Helper functions to use `array_map`.
-// Currently, array_map does not take closure as an argument, so we need to define a helper function.
-fn unzip_tup_interface(i: Valid<(U<INPUT_BITS>, Dir)>) -> (Valid<U<INPUT_BITS>>, Valid<Dir>) {
-    i.unzip()
+/// Systolic array of Transposer PEs.
+#[allow(clippy::type_complexity)]
+fn transposer_pes<const DIM: usize>(
+    in_row: [Valid<S<INPUT_BITS>>; DIM],
+    in_col_with_dir: [(Valid<S<INPUT_BITS>>, Valid<Dir>); DIM],
+) -> ([Valid<S<INPUT_BITS>>; DIM], [(Valid<S<INPUT_BITS>>, Valid<Dir>); DIM]) {
+    todo!("assignment 5")
 }
-fn extract_first(i: (Valid<U<INPUT_BITS>>, Valid<Dir>)) -> Valid<U<INPUT_BITS>> {
-    i.0
+
+/// Unzips the valid interfaces in the array.
+fn unzip_tuple_arr<P1: Copy, P2: Copy, const N: usize>(i: [Valid<(P1, P2)>; N]) -> [(Valid<P1>, Valid<P2>); N] {
+    // NOTE: The `array_map!` macro currently does not accept closures as arguments, so we explicitly used `Valid::<(P1, P2)>::unzip`
+    //       instead of `move |i| i.unzip()`.
+    array_map!(i, Valid::<(P1, P2)>::unzip)
+}
+
+/// Zips the valid interfaces in the array.
+fn zip_tuple_arr<P1: Copy, P2: Copy, const N: usize>(i: [(Valid<P1>, Valid<P2>); N]) -> [Valid<(P1, P2)>; N] {
+    // NOTE: The `array_map!` macro currently does not accept closures as arguments, so we explicitly used `JoinValidExt::join_valid`
+    //       instead of `move |(i1, i2)| (i1, i2).join_valid()`.
+    array_map!(i, JoinValidExt::join_valid)
 }
 
-/// Always out transposer.
-pub fn transposer<const DIM: usize>(_in_row: Valid<Array<U<INPUT_BITS>, DIM>>) -> Valid<Array<U<INPUT_BITS>, DIM>>
+/// Transposer.
+pub fn transposer<const DIM: usize>(i: Valid<Array<S<INPUT_BITS>, DIM>>) -> Valid<Array<S<INPUT_BITS>, DIM>>
 where
-    [(); max(clog2(DIM), 1)]:,
-    [(); max(clog2(DIM), 1) + 1]:,
+    [(); clog2(DIM)]:,
+    [(); clog2(DIM) + 1]:,
 {
     todo!("assignment 5")
 }
 
-/// Debug
+/// Transposer with default Gemmini configuration (16 x 16 Transposer PEs).
 #[synthesize]
-pub fn transposer_default(in_row: Valid<Array<U<INPUT_BITS>, 16>>) -> Valid<Array<U<INPUT_BITS>, 16>> {
+pub fn transposer_default(in_row: Valid<Array<S<INPUT_BITS>, 16>>) -> Valid<Array<S<INPUT_BITS>, 16>> {
     transposer::<16>(in_row)
 }

hazardflow-designs/src/gemmini/ffis.rs

@@ -30,7 +30,7 @@ pub fn mesh_ffi(in_left: MeshRowData, in_top: MeshColData) -> (MeshRowData, Mesh
 ///
 /// This module allows students to proceed with future assignments even if they have not completed assignment 5.
 #[magic(ffi::TransposerWrapper())]
-pub fn transposer_ffi(in_row: Valid<Array<U<INPUT_BITS>, 16>>) -> Valid<Array<U<INPUT_BITS>, 16>> {
+pub fn transposer_ffi(in_row: Valid<Array<S<INPUT_BITS>, 16>>) -> Valid<Array<S<INPUT_BITS>, 16>> {
     ffi!("TransposerWrapper.v")
 }
 

scripts/gemmini/unit_test.sh

@@ -10,14 +10,27 @@ if [[ $CONDA_DEFAULT_ENV == "base" ]]; then
     exit 1
 fi
 
+if [ "$1" == "pe" ]; then
+    TARGET_NAME="pe"
+elif [ "$1" == "mesh" ]; then
+    TARGET_NAME="mesh_default"
+elif [ "$1" == "transposer" ]; then
+    TARGET_NAME="transposer_default"
+elif [ "$1" == "mesh_with_delays" ]; then
+    TARGET_NAME="mwd"
+else
+    echo "Invalid argument. Please use \`pe\`, \`mesh\`, \`transposer\`, or \`mesh_with_delays\`."
+    exit 1
+fi
+
 # Current file absolute directory path
 CURR_DIR=$(cd `dirname $0` && pwd)
 LOG_FILE="cocotb_test.log"
 
 # 1. Compile the hazardflow module
 cd $CURR_DIR/../../
 rm -rf build/$1
-cargo r --release -- --target $1 --merge --system-task
+cargo r --release -- --target $TARGET_NAME --merge --system-task
 cd -
 
 pip3 install -r $CURR_DIR/requirements.txt

scripts/gemmini/unit_tests/mesh_default/Makefile → scripts/gemmini/unit_tests/mesh/Makefile

@@ -37,7 +37,7 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 
 DUT      = mesh_default
 TOPLEVEL = $(DUT)_top
-MODULE   = test_$(DUT)
+MODULE   = test_mesh
 VERILOG_SOURCES += ../../../../build/mesh_default/*.v
 VERILOG_SOURCES += ../../verilog_wrappers/PE256Wrapper.v
 VERILOG_SOURCES += ../../verilog_wrappers/PE_256.sv

scripts/gemmini/unit_tests/mwd/Makefile → scripts/gemmini/unit_tests/mesh_with_delays/Makefile

@@ -37,7 +37,7 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 
 DUT      = mwd
 TOPLEVEL = $(DUT)_top
-MODULE   = test_$(DUT)
+MODULE   = test_mesh_with_delays
 VERILOG_SOURCES += ../../../../build/mwd/*.v
 VERILOG_SOURCES += ../../verilog_wrappers/TransposerWrapper.v
 VERILOG_SOURCES += ../../verilog_wrappers/MeshWrapper.v

scripts/gemmini/unit_tests/pe/Makefile

@@ -37,7 +37,7 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 
 DUT      = pe
 TOPLEVEL = $(DUT)_top
-MODULE   = test_$(DUT)
+MODULE   = test_pe
 VERILOG_SOURCES += ../../../../build/pe/*.v
 PLUSARGS += -fst
 

scripts/gemmini/unit_tests/transposer/Makefile

@@ -37,7 +37,7 @@ COCOTB_HDL_TIMEPRECISION = 1ps
 
 DUT      = transposer_default
 TOPLEVEL = $(DUT)_top
-MODULE   = test_$(DUT)
+MODULE   = test_transposer
 VERILOG_SOURCES += ../../../../build/transposer_default/*.v
 PLUSARGS += -fst
 

scripts/gemmini/unit_tests/transposer/test_transposer_default.py → scripts/gemmini/unit_tests/transposer/test_transposer.py

@@ -23,10 +23,10 @@ def __init__(self, dut):
         cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
 
         self.in_row_valid = self.dut.in_input_0_payload_discriminant
-        self.in_row_data = self.dut.in_input_0_payload_Some_0
+        self.in_row_data = self.dut.in_input_0_payload_Some_0_0
 
         self.out_col_valid = self.dut.out_output_payload_discriminant
-        self.out_col_data = self.dut.out_output_payload_Some_0
+        self.out_col_data = self.dut.out_output_payload_Some_0_0
 
     async def reset(self):
         self.dut.rst.setimmediatevalue(0)

scripts/gemmini/verilog_wrappers/TransposerBlackBox.v

@@ -40,54 +40,54 @@ module TransposerBlackBox(
 );
 
     wire in_input_0_payload_discriminant;
-    wire [128-1:0] in_input_0_payload_Some_0;
+    wire [128-1:0] in_input_0_payload_Some_0_0;
     wire out_output_payload_discriminant;
-    wire [128-1:0] out_output_payload_Some_0;
+    wire [128-1:0] out_output_payload_Some_0_0;
 
     transposer_default_top transposer_default
     (
         .clk(clock),
         .rst(reset),
         .in_input_0_payload_discriminant(in_input_0_payload_discriminant),
-        .in_input_0_payload_Some_0(in_input_0_payload_Some_0),
+        .in_input_0_payload_Some_0_0(in_input_0_payload_Some_0_0),
         .out_output_payload_discriminant(out_output_payload_discriminant),
-        .out_output_payload_Some_0(out_output_payload_Some_0)
+        .out_output_payload_Some_0_0(out_output_payload_Some_0_0)
     );
 
     assign in_input_0_payload_discriminant = io_inRow_valid;
-    assign in_input_0_payload_Some_0[0 * 8 +: 8] = io_inRow_bits_0;
-    assign in_input_0_payload_Some_0[1 * 8 +: 8] = io_inRow_bits_1;
-    assign in_input_0_payload_Some_0[2 * 8 +: 8] = io_inRow_bits_2;
-    assign in_input_0_payload_Some_0[3 * 8 +: 8] = io_inRow_bits_3;
-    assign in_input_0_payload_Some_0[4 * 8 +: 8] = io_inRow_bits_4;
-    assign in_input_0_payload_Some_0[5 * 8 +: 8] = io_inRow_bits_5;
-    assign in_input_0_payload_Some_0[6 * 8 +: 8] = io_inRow_bits_6;
-    assign in_input_0_payload_Some_0[7 * 8 +: 8] = io_inRow_bits_7;
-    assign in_input_0_payload_Some_0[8 * 8 +: 8] = io_inRow_bits_8;
-    assign in_input_0_payload_Some_0[9 * 8 +: 8] = io_inRow_bits_9;
-    assign in_input_0_payload_Some_0[10 * 8 +: 8] = io_inRow_bits_10;
-    assign in_input_0_payload_Some_0[11 * 8 +: 8] = io_inRow_bits_11;
-    assign in_input_0_payload_Some_0[12 * 8 +: 8] = io_inRow_bits_12;
-    assign in_input_0_payload_Some_0[13 * 8 +: 8] = io_inRow_bits_13;
-    assign in_input_0_payload_Some_0[14 * 8 +: 8] = io_inRow_bits_14;
-    assign in_input_0_payload_Some_0[15 * 8 +: 8] = io_inRow_bits_15;
+    assign in_input_0_payload_Some_0_0[0 * 8 +: 8] = io_inRow_bits_0;
+    assign in_input_0_payload_Some_0_0[1 * 8 +: 8] = io_inRow_bits_1;
+    assign in_input_0_payload_Some_0_0[2 * 8 +: 8] = io_inRow_bits_2;
+    assign in_input_0_payload_Some_0_0[3 * 8 +: 8] = io_inRow_bits_3;
+    assign in_input_0_payload_Some_0_0[4 * 8 +: 8] = io_inRow_bits_4;
+    assign in_input_0_payload_Some_0_0[5 * 8 +: 8] = io_inRow_bits_5;
+    assign in_input_0_payload_Some_0_0[6 * 8 +: 8] = io_inRow_bits_6;
+    assign in_input_0_payload_Some_0_0[7 * 8 +: 8] = io_inRow_bits_7;
+    assign in_input_0_payload_Some_0_0[8 * 8 +: 8] = io_inRow_bits_8;
+    assign in_input_0_payload_Some_0_0[9 * 8 +: 8] = io_inRow_bits_9;
+    assign in_input_0_payload_Some_0_0[10 * 8 +: 8] = io_inRow_bits_10;
+    assign in_input_0_payload_Some_0_0[11 * 8 +: 8] = io_inRow_bits_11;
+    assign in_input_0_payload_Some_0_0[12 * 8 +: 8] = io_inRow_bits_12;
+    assign in_input_0_payload_Some_0_0[13 * 8 +: 8] = io_inRow_bits_13;
+    assign in_input_0_payload_Some_0_0[14 * 8 +: 8] = io_inRow_bits_14;
+    assign in_input_0_payload_Some_0_0[15 * 8 +: 8] = io_inRow_bits_15;
 
-    assign io_outCol_bits_0 = out_output_payload_Some_0[0 * 8 +: 8];
-    assign io_outCol_bits_1 = out_output_payload_Some_0[1 * 8 +: 8];
-    assign io_outCol_bits_2 = out_output_payload_Some_0[2 * 8 +: 8];
-    assign io_outCol_bits_3 = out_output_payload_Some_0[3 * 8 +: 8];
-    assign io_outCol_bits_4 = out_output_payload_Some_0[4 * 8 +: 8];
-    assign io_outCol_bits_5 = out_output_payload_Some_0[5 * 8 +: 8];
-    assign io_outCol_bits_6 = out_output_payload_Some_0[6 * 8 +: 8];
-    assign io_outCol_bits_7 = out_output_payload_Some_0[7 * 8 +: 8];
-    assign io_outCol_bits_8 = out_output_payload_Some_0[8 * 8 +: 8];
-    assign io_outCol_bits_9 = out_output_payload_Some_0[9 * 8 +: 8];
-    assign io_outCol_bits_10 = out_output_payload_Some_0[10 * 8 +: 8];
-    assign io_outCol_bits_11 = out_output_payload_Some_0[11 * 8 +: 8];
-    assign io_outCol_bits_12 = out_output_payload_Some_0[12 * 8 +: 8];
-    assign io_outCol_bits_13 = out_output_payload_Some_0[13 * 8 +: 8];
-    assign io_outCol_bits_14 = out_output_payload_Some_0[14 * 8 +: 8];
-    assign io_outCol_bits_15 = out_output_payload_Some_0[15 * 8 +: 8];
+    assign io_outCol_bits_0 = out_output_payload_Some_0_0[0 * 8 +: 8];
+    assign io_outCol_bits_1 = out_output_payload_Some_0_0[1 * 8 +: 8];
+    assign io_outCol_bits_2 = out_output_payload_Some_0_0[2 * 8 +: 8];
+    assign io_outCol_bits_3 = out_output_payload_Some_0_0[3 * 8 +: 8];
+    assign io_outCol_bits_4 = out_output_payload_Some_0_0[4 * 8 +: 8];
+    assign io_outCol_bits_5 = out_output_payload_Some_0_0[5 * 8 +: 8];
+    assign io_outCol_bits_6 = out_output_payload_Some_0_0[6 * 8 +: 8];
+    assign io_outCol_bits_7 = out_output_payload_Some_0_0[7 * 8 +: 8];
+    assign io_outCol_bits_8 = out_output_payload_Some_0_0[8 * 8 +: 8];
+    assign io_outCol_bits_9 = out_output_payload_Some_0_0[9 * 8 +: 8];
+    assign io_outCol_bits_10 = out_output_payload_Some_0_0[10 * 8 +: 8];
+    assign io_outCol_bits_11 = out_output_payload_Some_0_0[11 * 8 +: 8];
+    assign io_outCol_bits_12 = out_output_payload_Some_0_0[12 * 8 +: 8];
+    assign io_outCol_bits_13 = out_output_payload_Some_0_0[13 * 8 +: 8];
+    assign io_outCol_bits_14 = out_output_payload_Some_0_0[14 * 8 +: 8];
+    assign io_outCol_bits_15 = out_output_payload_Some_0_0[15 * 8 +: 8];
 
     assign io_inRow_ready = 1'b1;
     assign io_outCol_valid = 1'b1;

scripts/gemmini/verilog_wrappers/TransposerWrapper.v

@@ -4,49 +4,49 @@ module TransposerWrapper
     input wire rst,
 
     input wire in_input_0_payload_discriminant,
-    input wire [128-1:0] in_input_0_payload_Some_0,
+    input wire [128-1:0] in_input_0_payload_Some_0_0,
 
     output wire out_output_payload_discriminant,
-    output wire [128-1:0] out_output_payload_Some_0
+    output wire [128-1:0] out_output_payload_Some_0_0
 );  
     AlwaysOutTransposer always_out_transposer_inst(
         .clock(clk),
         .reset(rst),
 
         .io_inRow_valid(in_input_0_payload_discriminant),
-        .io_inRow_bits_0(in_input_0_payload_Some_0[0*8 +: 8]),
-        .io_inRow_bits_1(in_input_0_payload_Some_0[1*8 +: 8]),
-        .io_inRow_bits_2(in_input_0_payload_Some_0[2*8 +: 8]),
-        .io_inRow_bits_3(in_input_0_payload_Some_0[3*8 +: 8]),
-        .io_inRow_bits_4(in_input_0_payload_Some_0[4*8 +: 8]),
-        .io_inRow_bits_5(in_input_0_payload_Some_0[5*8 +: 8]),
-        .io_inRow_bits_6(in_input_0_payload_Some_0[6*8 +: 8]),
-        .io_inRow_bits_7(in_input_0_payload_Some_0[7*8 +: 8]),
-        .io_inRow_bits_8(in_input_0_payload_Some_0[8*8 +: 8]),
-        .io_inRow_bits_9(in_input_0_payload_Some_0[9*8 +: 8]),
-        .io_inRow_bits_10(in_input_0_payload_Some_0[10*8 +: 8]),
-        .io_inRow_bits_11(in_input_0_payload_Some_0[11*8 +: 8]),
-        .io_inRow_bits_12(in_input_0_payload_Some_0[12*8 +: 8]),
-        .io_inRow_bits_13(in_input_0_payload_Some_0[13*8 +: 8]),
-        .io_inRow_bits_14(in_input_0_payload_Some_0[14*8 +: 8]),
-        .io_inRow_bits_15(in_input_0_payload_Some_0[15*8 +: 8]),
+        .io_inRow_bits_0(in_input_0_payload_Some_0_0[0*8 +: 8]),
+        .io_inRow_bits_1(in_input_0_payload_Some_0_0[1*8 +: 8]),
+        .io_inRow_bits_2(in_input_0_payload_Some_0_0[2*8 +: 8]),
+        .io_inRow_bits_3(in_input_0_payload_Some_0_0[3*8 +: 8]),
+        .io_inRow_bits_4(in_input_0_payload_Some_0_0[4*8 +: 8]),
+        .io_inRow_bits_5(in_input_0_payload_Some_0_0[5*8 +: 8]),
+        .io_inRow_bits_6(in_input_0_payload_Some_0_0[6*8 +: 8]),
+        .io_inRow_bits_7(in_input_0_payload_Some_0_0[7*8 +: 8]),
+        .io_inRow_bits_8(in_input_0_payload_Some_0_0[8*8 +: 8]),
+        .io_inRow_bits_9(in_input_0_payload_Some_0_0[9*8 +: 8]),
+        .io_inRow_bits_10(in_input_0_payload_Some_0_0[10*8 +: 8]),
+        .io_inRow_bits_11(in_input_0_payload_Some_0_0[11*8 +: 8]),
+        .io_inRow_bits_12(in_input_0_payload_Some_0_0[12*8 +: 8]),
+        .io_inRow_bits_13(in_input_0_payload_Some_0_0[13*8 +: 8]),
+        .io_inRow_bits_14(in_input_0_payload_Some_0_0[14*8 +: 8]),
+        .io_inRow_bits_15(in_input_0_payload_Some_0_0[15*8 +: 8]),
 
-        .io_outCol_bits_0(out_output_payload_Some_0[0*8 +: 8]),
-        .io_outCol_bits_1(out_output_payload_Some_0[1*8 +: 8]),
-        .io_outCol_bits_2(out_output_payload_Some_0[2*8 +: 8]),
-        .io_outCol_bits_3(out_output_payload_Some_0[3*8 +: 8]),
-        .io_outCol_bits_4(out_output_payload_Some_0[4*8 +: 8]),
-        .io_outCol_bits_5(out_output_payload_Some_0[5*8 +: 8]),
-        .io_outCol_bits_6(out_output_payload_Some_0[6*8 +: 8]),
-        .io_outCol_bits_7(out_output_payload_Some_0[7*8 +: 8]),
-        .io_outCol_bits_8(out_output_payload_Some_0[8*8 +: 8]),
-        .io_outCol_bits_9(out_output_payload_Some_0[9*8 +: 8]),
-        .io_outCol_bits_10(out_output_payload_Some_0[10*8 +: 8]),
-        .io_outCol_bits_11(out_output_payload_Some_0[11*8 +: 8]),
-        .io_outCol_bits_12(out_output_payload_Some_0[12*8 +: 8]),
-        .io_outCol_bits_13(out_output_payload_Some_0[13*8 +: 8]),
-        .io_outCol_bits_14(out_output_payload_Some_0[14*8 +: 8]),
-        .io_outCol_bits_15(out_output_payload_Some_0[15*8 +: 8])
+        .io_outCol_bits_0(out_output_payload_Some_0_0[0*8 +: 8]),
+        .io_outCol_bits_1(out_output_payload_Some_0_0[1*8 +: 8]),
+        .io_outCol_bits_2(out_output_payload_Some_0_0[2*8 +: 8]),
+        .io_outCol_bits_3(out_output_payload_Some_0_0[3*8 +: 8]),
+        .io_outCol_bits_4(out_output_payload_Some_0_0[4*8 +: 8]),
+        .io_outCol_bits_5(out_output_payload_Some_0_0[5*8 +: 8]),
+        .io_outCol_bits_6(out_output_payload_Some_0_0[6*8 +: 8]),
+        .io_outCol_bits_7(out_output_payload_Some_0_0[7*8 +: 8]),
+        .io_outCol_bits_8(out_output_payload_Some_0_0[8*8 +: 8]),
+        .io_outCol_bits_9(out_output_payload_Some_0_0[9*8 +: 8]),
+        .io_outCol_bits_10(out_output_payload_Some_0_0[10*8 +: 8]),
+        .io_outCol_bits_11(out_output_payload_Some_0_0[11*8 +: 8]),
+        .io_outCol_bits_12(out_output_payload_Some_0_0[12*8 +: 8]),
+        .io_outCol_bits_13(out_output_payload_Some_0_0[13*8 +: 8]),
+        .io_outCol_bits_14(out_output_payload_Some_0_0[14*8 +: 8]),
+        .io_outCol_bits_15(out_output_payload_Some_0_0[15*8 +: 8])
     );
 
     assign out_output_payload_discriminant = 1'b1;