Ported pyrpl to be based on RP OS 2.00, using our scripts, changed BD…

… to that of v0.94.
juretrn · May 29, 2024 · 189568b · 189568b
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diff --git a/Makefile.x86 b/Makefile.x86
diff --git a/pyrpl/fpga/Makefile b/pyrpl/fpga/Makefile
@@ -1,32 +1,69 @@
-#######################################
 #
 # Authors: Matej Oblak, Iztok Jeras
 # (C) Red Pitaya 2013-2015
 #
-# Red Pitaya FPGA/SoC Makefile 
+# Red Pitaya FPGA/SoC Makefile
 #
+# Produces:
+#   3. FPGA bit file.
+#   1. FSBL (First stage bootloader) ELF binary.
+#   2. Memtest (stand alone memory test) ELF binary.
+#   4. Linux device tree source (dts).
 
-# build results
-FPGA_BIN=out/red_pitaya.bin
+PRJ   ?= logic
+MODEL ?= Z10
+HWID  ?= ""
+DEFINES ?= ""
+DTS_VER ?= 2017.2
 
-#logfile for stdout and stderr
-LOG=>> fpga.log 2>&1
+# build artefacts
+FPGA_BIT    = prj/$(PRJ)/out/red_pitaya.bit
+FPGA_BIN    = prj/$(PRJ)/out/red_pitaya.bit.bin
+FSBL_ELF    = prj/$(PRJ)/sdk/fsbl/executable.elf
+MEMTEST_ELF = prj/$(PRJ)/sdk/dram_test/executable.elf
+DEVICE_TREE = prj/$(PRJ)/sdk/dts/system.dts
 
 # Vivado from Xilinx provides IP handling, FPGA compilation
 # hsi (hardware software interface) provides software integration
 # both tools are run in batch mode with an option to avoid log/journal files
-VIVADO = vivado -nolog -nojournal -mode batch
+VIVADO = vivado -nojournal -mode batch
+HSI    = hsi    -nolog -nojournal -mode batch
+BOOTGEN= bootgen -image prj/$(PRJ)/out/red_pitaya.bif -arch zynq -process_bitstream bin
+#HSI    = hsi    -nolog -mode batch
 
-all: clean $(FPGA_BIN) postclean
+.PHONY: all clean project sim
 
+all: $(FPGA_BIT) $(FSBL_ELF) $(DEVICE_TREE) $(FPGA_BIN)
+
+# TODO: clean should go into each project
 clean:
-	rm -rf out .Xil .srcs sdk
+	rm -rf out .Xil .srcs sdk project sim
+	rm -rf prj/$(PRJ)/out prj/$(PRJ)/.Xil prj/$(PRJ)/.srcs prj/$(PRJ)/sdk prj/$(PRJ)/project
+
+sim: 
+	vivado -source red_pitaya_vivado_sim.tcl -tclargs $(PRJ) $(MODEL) $(DEFINES)
+
+project:
+ifneq ($(HWID),"")
+	vivado -source red_pitaya_vivado_project_$(MODEL).tcl -tclargs $(PRJ) $(DEFINES) HWID=$(HWID)
+else
+	vivado -source red_pitaya_vivado_project_$(MODEL).tcl -tclargs $(PRJ) $(DEFINES)
+endif
+
+$(FPGA_BIT):
+ifneq ($(HWID),"")
+	$(VIVADO) -source red_pitaya_vivado_$(MODEL).tcl -tclargs $(PRJ) $(DEFINES) HWID=$(HWID)
+else
+	$(VIVADO) -source red_pitaya_vivado_$(MODEL).tcl -tclargs $(PRJ) $(DEFINES)
+endif
+	./synCheck.sh
+
+$(FSBL_ELF): $(FPGA_BIT)
+	xsct red_pitaya_hsi_fsbl.tcl $(PRJ)
 
-$(FPGA_BIN):
-	$(VIVADO) -source red_pitaya_vivado.tcl $(LOG)
+$(DEVICE_TREE): $(FPGA_BIT)
+	xsct red_pitaya_hsi_dts.tcl  $(PRJ) DTS_VER=$(DTS_VER)
 
-postclean:
-	mv *.xml out/
-	mv *.prm out/
-	mv *.html out/
-	mv *.log out/
+$(FPGA_BIN): $(FPGA_BIT)
+	@echo all:{$(FPGA_BIT)} > prj/$(PRJ)/out/red_pitaya.bif
+	$(BOOTGEN)
diff --git a/pyrpl/fpga/dts/clkc.dtsi b/pyrpl/fpga/dts/clkc.dtsi
@@ -0,0 +1,7 @@
+/*
+ * PL clock configuration
+ */
+
+&clkc {
+	fclk-enable = <0xf>;
+};
diff --git a/pyrpl/fpga/dts/ethernet.dtsi b/pyrpl/fpga/dts/ethernet.dtsi
@@ -0,0 +1,10 @@
+/*
+ * Lantiq ethernet PHY 
+ */
+
+&gem0 {
+	phy-handle = <&ethernet_0_mdio>;
+	ethernet_0_mdio: ethernet_0_mdio@1 {
+		reg = <1>;
+	};
+};
diff --git a/pyrpl/fpga/dts/gpio.dtsi b/pyrpl/fpga/dts/gpio.dtsi
@@ -0,0 +1,86 @@
+/*
+ * GPIO names
+ */
+
+&gpio0 {
+	gpio-line-names =
+		"MIO0 (LED 8)",
+		"MIO1 (QSPI_CS#)",
+		"MIO2 (QSPI_IO0)",
+		"MIO3 (QSPI_IO1)",
+		"MIO4 (QSPI_IO2)",
+		"MIO5 (QSPI_IO3)",
+		"MIO6 (QSPI_CLK)",
+		"MIO7 (LED 9)",
+		"MIO8 (UART1_TX)",
+		"MIO9 (UART1_RX)",
+		"MIO10 (SPI1_MOSI)",
+		"MIO11 (SPI1_MISO)",
+		"MIO12 (SPI1_CLK)",
+		"MIO13 (SPI1_CS#)",
+		"MIO14 (UART0_RX)",
+		"MIO15 (UART0_TX)",
+		"MIO16 (ETH_TXCLK)",
+		"MIO17 (ETH_TXD0)",
+		"MIO18 (ETH_TXD1)",
+		"MIO19 (ETH_TXD2)",
+		"MIO20 (ETH_TXD3)",
+		"MIO21 (ETH_TXCTL)",
+		"MIO22 (ETH_RXCLK)",
+		"MIO23 (ETH_RXD0)",
+		"MIO24 (ETH_RXD1)",
+		"MIO25 (ETH_RXD2)",
+		"MIO26 (ETH_RXD3)",
+		"MIO27 (ETH_RXCTL)",
+		"MIO28 (USB_D4)",
+		"MIO29 (USB_DIR)",
+		"MIO30 (USB_STP)",
+		"MIO31 (USB_NXT)",
+		"MIO32 (USB_D0)",
+		"MIO33 (USB_D1)",
+		"MIO34 (USB_D2)",
+		"MIO35 (USB_D3)",
+		"MIO36 (USB_CLK)",
+		"MIO37 (USB_D5)",
+		"MIO38 (USB_D6)",
+		"MIO39 (USB_D7)",
+		"MIO40 (SDIO_CLK)",
+		"MIO41 (SDIO_CMD)",
+		"MIO42 (SDIO_DAT0)",
+		"MIO43 (SDIO_DAT1)",
+		"MIO44 (SDIO_DAT2)",
+		"MIO45 (SDIO_DAT3)",
+		"MIO46 (SDIO_SDDET)",
+		"MIO47 (SDIO_WP)",
+		"MIO48 (USB_RESB)",
+		"MIO49 (USB_FLG)",
+		"MIO50 (I2C0_SDA)",
+		"MIO51 (I2C0_SCL)",
+		"MIO52 (ETH_MDC)",
+		"MIO53 (ETH_MDIO)",
+		"EMIO0 (LED 0)",
+		"EMIO1 (LED 1)",
+		"EMIO2 (LED 2)",
+		"EMIO3 (LED 3)",
+		"EMIO4 (LED 4)",
+		"EMIO5 (LED 5)",
+		"EMIO6 (LED 6)",
+		"EMIO7 (LED 7)",
+		"EMIO8  (GPIO 0)",
+		"EMIO9  (GPIO 1)",
+		"EMIO10 (GPIO 2)",
+		"EMIO11 (GPIO 3)",
+		"EMIO12 (GPIO 4)",
+		"EMIO13 (GPIO 5)",
+		"EMIO14 (GPIO 6)",
+		"EMIO15 (GPIO 7)",
+		"EMIO16 (GPIO 8)",
+		"EMIO17 (GPIO 9)",
+		"EMIO18 (GPIO 10)",
+		"EMIO19 (GPIO 11)",
+		"EMIO20 (GPIO 12)",
+		"EMIO21 (GPIO 13)",
+		"EMIO22 (GPIO 14)",
+		"EMIO23 (GPIO 15)",
+		"EMIO24 (GPIO 16)";
+};
diff --git a/pyrpl/fpga/dts/i2c0.dtsi b/pyrpl/fpga/dts/i2c0.dtsi
@@ -0,0 +1,17 @@
+/*
+ * list devices on I2C bus
+ */
+
+&i2c0 {
+	eeprom@50 {
+		compatible = "24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	eeprom@51 {
+		compatible = "24c64";
+		reg = <0x51>;
+		pagesize = <32>;
+	};
+};
diff --git a/pyrpl/fpga/dts/i2c2gpio.dtsi b/pyrpl/fpga/dts/i2c2gpio.dtsi
@@ -0,0 +1,24 @@
+&pinctrl0 {
+	pinctrl_i2c2gpio: i2c2gpio {
+		mux {
+			function = "gpio0";
+			groups = "gpio0_50_grp", "gpio0_51_grp";
+		};
+
+		conf {
+			groups = "gpio0_50_grp", "gpio0_51_grp";
+			slew-rate = <0>;
+			io-standard = <2>;  // LVCMOS25
+		};
+
+		conf-pull-none {
+			pins = "MIO50", "MIO51";
+			bias-disable;
+		};
+	};
+};
+
+&gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2gpio>;
+};
diff --git a/pyrpl/fpga/dts/led-system.dtsi b/pyrpl/fpga/dts/led-system.dtsi
@@ -0,0 +1,23 @@
+/*
+ * stystem LED are given a fixed function
+ * yellow LED - SD card access
+ * red    LED - CPU heartbeat
+ */
+
+/ {
+	led-system {
+		compatible = "gpio-leds";
+		led-8-yellow {
+			label = "led8";
+			gpios = <&gpio0 0 0>;
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+		led-9-red {
+			label = "led9";
+			gpios = <&gpio0 7 0>;
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
diff --git a/pyrpl/fpga/dts/led-user.dtsi b/pyrpl/fpga/dts/led-user.dtsi
@@ -0,0 +1,49 @@
+/*
+ * user LED
+ */
+
+/ {
+	led-user {
+		compatible = "gpio-leds";
+		led-0-yellow {
+			label = "led0";
+			gpios = <&gpio0 54 0>;
+			default-state = "off";
+		};
+		led-1-yellow {
+			label = "led1";
+			gpios = <&gpio0 55 0>;
+			default-state = "off";
+		};
+		led-2-yellow {
+			label = "led2";
+			gpios = <&gpio0 56 0>;
+			default-state = "off";
+		};
+		led-3-yellow {
+			label = "led3";
+			gpios = <&gpio0 57 0>;
+			default-state = "off";
+		};
+		led-4-yellow {
+			label = "led4";
+			gpios = <&gpio0 58 0>;
+			default-state = "off";
+		};
+		led-5-yellow {
+			label = "led5";
+			gpios = <&gpio0 59 0>;
+			default-state = "off";
+		};
+		led-6-yellow {
+			label = "led6";
+			gpios = <&gpio0 60 0>;
+			default-state = "off";
+		};
+		led-7-yellow {
+			label = "led7";
+			gpios = <&gpio0 61 0>;
+			default-state = "off";
+		};
+	};
+};
diff --git a/pyrpl/fpga/dts/led-user.dtso b/pyrpl/fpga/dts/led-user.dtso
@@ -0,0 +1,56 @@
+/*
+ * user LED
+*/
+
+/ {
+	fragment@led-user {
+		target-path="/";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		__overlay__ {
+			led-user {
+				compatible = "gpio-leds";
+				led-0-yellow {
+					label = "led0";
+					gpios = <&gpio0 54 0>;
+					default-state = "off";
+				};
+				led-1-yellow {
+					label = "led1";
+					gpios = <&gpio0 55 0>;
+					default-state = "off";
+				};
+				led-2-yellow {
+					label = "led2";
+					gpios = <&gpio0 56 0>;
+					default-state = "off";
+				};
+				led-3-yellow {
+					label = "led3";
+					gpios = <&gpio0 57 0>;
+					default-state = "off";
+				};
+				led-4-yellow {
+					label = "led4";
+					gpios = <&gpio0 58 0>;
+					default-state = "off";
+				};
+				led-5-yellow {
+					label = "led5";
+					gpios = <&gpio0 59 0>;
+					default-state = "off";
+				};
+				led-6-yellow {
+					label = "led6";
+					gpios = <&gpio0 60 0>;
+					default-state = "off";
+				};
+				led-7-yellow {
+					label = "led7";
+					gpios = <&gpio0 61 0>;
+					default-state = "off";
+				};
+			};
+		};
+	};
+};
diff --git a/pyrpl/fpga/dts/memory.dtsi b/pyrpl/fpga/dts/memory.dtsi
@@ -0,0 +1,27 @@
+/*
+ * define memory for DMA pool
+ */
+
+/ {
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x1000000>;
+			alignment = <0x2000>;
+			linux,cma-default;
+		};
+		rprx_reserverd: labuf@a000000 {
+			/*compatible = "redpitaya,rprx-memory";*/
+			reg = <0xa000000 0x2000000>;
+		};
+
+		dma_region: buffer@1000000 {
+			reg = <0x1000000 0x200000>;
+		};
+
+	};
+};