FPGA Repository

Source the shell script to add yosys to path

Todo

• Create reusable/common directory
• Create modules
  • Systemverilog
    • Systemverilog register map (with simple accessors for other modules)
    • Interface example
  • Devices
    • generic SPI peripheral (target)
    • generic I2C target
    • generic UART target
• DSP
  • FIR example
  • Lamda (IIR) example
  • Sine Loopkup table
  • Frequency sweep (0 to Fs/2)
  • Audio examples