big cleanup

- show word size
- remove cmdline= from -semihosting-config
- use CONFIG_GNU_ARM_ECLIPSE for all specific code
- bring pixman module back, but do not use it
- clean armv7m.c and move code to cortexm.c

.gitmodules

@@ -22,6 +22,9 @@
 [submodule "roms/sgabios"]
 	path = roms/sgabios
 	url = git://git.qemu-project.org/sgabios.git
+[submodule "pixman"]
+	path = pixman
+	url = git://anongit.freedesktop.org/pixman
 [submodule "dtc"]
 	path = dtc
 	url = git://git.qemu-project.org/dtc.git

Makefile

@@ -534,7 +534,6 @@ endif
 installer: $(INSTALLER)
 
 INSTDIR=/tmp/qemu-nsis
-QEMU_NSI_FILE=$(SRC_PATH)/qemu.nsi
 
 $(INSTALLER): $(SRC_PATH)/qemu.nsi
 	$(MAKE) install prefix=${INSTDIR}
@@ -562,7 +561,7 @@ endif # SIGNCODE
                 $(if $(DLL_PATH),-DDLLDIR="$(DLL_PATH)") \
                 -DSRCDIR="$(SRC_PATH)" \
                 -DOUTFILE="$(INSTALLER)" \
-                $(QEMU_NSI_FILE)
+                $(SRC_PATH)/qemu.nsi
 	rm -r ${INSTDIR}
 ifdef SIGNCODE
 	$(SIGNCODE) $(INSTALLER)

default-configs/arm-softmmu.mak

@@ -18,12 +18,14 @@ CONFIG_TMP105=y
 CONFIG_STELLARIS=y
 CONFIG_STELLARIS_INPUT=y
 CONFIG_STELLARIS_ENET=y
+# [GNU ARM Eclipse]
 CONFIG_STM32=y
 CONFIG_KINETIS=y
 CONFIG_LPC=y
 CONFIG_TIVA=y
 CONFIG_XMC=y
 CONFIG_SAM=y
+# [GNU ARM Eclipse]
 CONFIG_SSD0303=y
 CONFIG_SSD0323=y
 CONFIG_ADS7846=y

hw/arm/Makefile.objs

@@ -12,6 +12,7 @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
 obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
 
 
+# [GNU ARM Eclipse]
 # Cortex-M files
 obj-y += cortexm.o
 obj-$(CONFIG_STM32) += stm32_mcus.o stm32_boards.o stm32_olimex_boards.o
@@ -21,3 +22,4 @@ obj-$(CONFIG_LPC) += lpc_mcus.o lpc_boards.o
 obj-$(CONFIG_TIVA) += tiva_mcus.o tiva_boards.o
 obj-$(CONFIG_XMC) += xmc_mcus.o xmc_boards.o
 obj-$(CONFIG_SAM) += sam_mcus.o sam_boards.o
+# [GNU ARM Eclipse]

hw/arm/armv7m.c

@@ -14,15 +14,6 @@
 #include "sysemu/qtest.h"
 #include "qemu/error-report.h"
 
-#if defined(CONFIG_GNU_ARM_ECLIPSE)
-#include "config.h"
-#include "sysemu/sysemu.h"
-#include "hw/arm/cortexm.h"
-#include "hw/boards.h"
-
-static struct arm_boot_info armv7m_binfo;
-#endif /* defined(CONFIG_GNU_ARM_ECLIPSE) */
-
 /* Bitbanded IO.  Each word corresponds to a single bit.  */
 
 /* Get the byte address of the real memory for a bitband access.  */
@@ -175,122 +166,6 @@ static void armv7m_reset(void *opaque)
    mem_size is in bytes.
    Returns the NVIC array.  */
 
-#if defined(CONFIG_GNU_ARM_ECLIPSE)
-
-/* Init CPU and memory for a v7-M based board.
- flash_size and sram_size are in kb.
- Returns the NVIC array.  */
-
-qemu_irq *cortexm_armv7m_init(MemoryRegion *system_memory,
-                      int flash_size, int sram_size,
-                      MachineState *machine)
-{
-    ARMCPU *cpu;
-    CPUARMState *env;
-    DeviceState *nvic;
-    /* FIXME: make this local state.  */
-    static qemu_irq pic[64];
-    int image_size;
-    uint64_t entry;
-    uint64_t lowaddr;
-    int i;
-    int big_endian;
-    MemoryRegion *sram = g_new(MemoryRegion, 1);
-    MemoryRegion *flash = g_new(MemoryRegion, 1);
-    MemoryRegion *hack = g_new(MemoryRegion, 1);
-
-    const char *kernel_filename = machine->kernel_filename;
-    const char *kernel_cmdline = machine->kernel_cmdline;
-    const char *cpu_model = machine->cpu_model;
-
-    flash_size *= 1024;
-    sram_size *= 1024;
-
-    if (cpu_model == NULL) {
-        cpu_model = "cortex-m3";
-    }
-    cpu = cpu_arm_init(cpu_model);
-    if (cpu == NULL) {
-        fprintf(stderr, "Unable to find CPU definition %s\n", cpu_model);
-        exit(1);
-    }
-    env = &cpu->env;
-
-#if 0
-    /* > 32Mb SRAM gets complicated because it overlaps the bitband area.
-     We don't have proper commandline options, so allocate half of memory
-     as SRAM, up to a maximum of 32Mb, and the rest as code.  */
-    if (ram_size > (512 + 32) * 1024 * 1024)
-    ram_size = (512 + 32) * 1024 * 1024;
-    sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
-    if (sram_size > 32 * 1024 * 1024)
-    sram_size = 32 * 1024 * 1024;
-    code_size = ram_size - sram_size;
-#endif
-
-    /* Flash programming is done via the SCU, so pretend it is ROM.  */
-    memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size,
-                           &error_abort);
-    vmstate_register_ram_global(flash);
-    memory_region_set_readonly(flash, true);
-    memory_region_add_subregion(system_memory, 0, flash);
-    memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size, &error_abort);
-    vmstate_register_ram_global(sram);
-    memory_region_add_subregion(system_memory, 0x20000000, sram);
-    armv7m_bitband_init();
-
-    nvic = qdev_create(NULL, "armv7m_nvic");
-    env->nvic = nvic;
-    qdev_init_nofail(nvic);
-    sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
-                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
-    for (i = 0; i < 64; i++) {
-        pic[i] = qdev_get_gpio_in(nvic, i);
-    }
-
-#ifdef TARGET_WORDS_BIGENDIAN
-    big_endian = 1;
-#else
-    big_endian = 0;
-#endif
-
-    if (!kernel_filename && !qtest_enabled() && !with_gdb) {
-        fprintf(stderr, "Guest image must be specified (using -kernel)\n");
-        exit(1);
-    }
-
-    /* Fill-in a minimalistic boot info, required for semihosting.  */
-    armv7m_binfo.kernel_cmdline = kernel_cmdline;
-    armv7m_binfo.kernel_filename = machine->kernel_cmdline;
-
-    env->boot_info = &armv7m_binfo;
-
-    if (kernel_filename) {
-        image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
-                              NULL, big_endian, ELF_MACHINE, 1);
-        if (image_size < 0) {
-            image_size = load_image_targphys(kernel_filename, 0, flash_size);
-            lowaddr = 0;
-        }
-        if (image_size < 0) {
-            error_report("Could not load kernel '%s'", kernel_filename);
-            exit(1);
-        }
-    }
-
-    /* Hack to map an additional page of ram at the top of the address
-     space.  This stops qemu complaining about executing code outside RAM
-     when returning from an exception.  */
-    memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000, &error_abort);
-    vmstate_register_ram_global(hack);
-    memory_region_add_subregion(system_memory, 0xfffff000, hack);
-
-    qemu_register_reset(armv7m_reset, cpu);
-    return pic;
-}
-
-#endif /* defined(CONFIG_GNU_ARM_ECLIPSE) */
-
 qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
                       const char *kernel_filename, const char *cpu_model)
 {

hw/arm/cortexm.c

@@ -1,17 +1,44 @@
 /*
- * Cortex-M System emulation
+ * Cortex-M System emulation.
  *
  * Copyright (c) 2014 Liviu Ionescu
  *
  * This code is licensed under the GPL.
  */
 
-#include "hw/arm/cortexm.h"
+#include "config.h"
 #include "sysemu/sysemu.h"
+#include "hw/arm/cortexm.h"
 #include "qemu/option.h"
 #include "qemu/config-file.h"
 #include "hw/arm/arm.h"
 #include "exec/address-spaces.h"
+#include "hw/sysbus.h"
+#include "qemu/error-report.h"
+#include "sysemu/qtest.h"
+#include "hw/loader.h"
+#include "elf.h"
+
+/* Redefined from armv7m.c */
+#define TYPE_BITBAND "ARM,bitband-memory"
+
+static void cortexm_reset(void *opaque);
+
+static void cortexm_bitband_init(void)
+{
+    DeviceState *dev;
+
+    dev = qdev_create(NULL, TYPE_BITBAND);
+    qdev_prop_set_uint32(dev, "base", 0x20000000);
+    qdev_init_nofail(dev);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x22000000);
+
+    dev = qdev_create(NULL, TYPE_BITBAND);
+    qdev_prop_set_uint32(dev, "base", 0x40000000);
+    qdev_init_nofail(dev);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x42000000);
+}
+
 
 /* Common Cortex-M core initialisation routine.  */
 qemu_irq *cortex_m_core_init(cortex_m_core_info *cm_info, MachineState *machine)
@@ -56,8 +83,108 @@ qemu_irq *cortex_m_core_init(cortex_m_core_info *cm_info, MachineState *machine)
     if (system_memory == NULL) {
         system_memory = get_system_memory();
     }
-    qemu_irq *pic;
-    pic = cortexm_armv7m_init(system_memory, flash_size_kb, sram_size_kb, machine);
+
+    int flash_size = flash_size_kb * 1024;
+    int sram_size = sram_size_kb * 1024;
+    ARMCPU *cpu;
+    CPUARMState *env;
+    DeviceState *nvic;
+    /* FIXME: make this local state.  */
+    static qemu_irq pic[64];
+    static struct arm_boot_info cortexm_binfo;
+    int image_size;
+    uint64_t entry;
+    uint64_t lowaddr;
+    int i;
+    int big_endian;
+    MemoryRegion *sram = g_new(MemoryRegion, 1);
+    MemoryRegion *flash = g_new(MemoryRegion, 1);
+    MemoryRegion *hack = g_new(MemoryRegion, 1);
+
+    const char *kernel_filename = machine->kernel_filename;
+    const char *kernel_cmdline = machine->kernel_cmdline;
+    const char *cpu_model = machine->cpu_model;
+
+    if (cpu_model == NULL) {
+        cpu_model = "cortex-m3";
+    }
+    cpu = cpu_arm_init(cpu_model);
+    if (cpu == NULL) {
+        fprintf(stderr, "Unable to find CPU definition %s\n", cpu_model);
+        exit(1);
+    }
+    env = &cpu->env;
+
+#if 0
+    /* > 32Mb SRAM gets complicated because it overlaps the bitband area.
+     We don't have proper commandline options, so allocate half of memory
+     as SRAM, up to a maximum of 32Mb, and the rest as code.  */
+    if (ram_size > (512 + 32) * 1024 * 1024)
+    ram_size = (512 + 32) * 1024 * 1024;
+    sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
+    if (sram_size > 32 * 1024 * 1024)
+    sram_size = 32 * 1024 * 1024;
+    code_size = ram_size - sram_size;
+#endif
+
+    /* Flash programming is done via the SCU, so pretend it is ROM.  */
+    memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size,
+                           &error_abort);
+    vmstate_register_ram_global(flash);
+    memory_region_set_readonly(flash, true);
+    memory_region_add_subregion(system_memory, 0, flash);
+    memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size, &error_abort);
+    vmstate_register_ram_global(sram);
+    memory_region_add_subregion(system_memory, 0x20000000, sram);
+    cortexm_bitband_init();
+
+    nvic = qdev_create(NULL, "armv7m_nvic");
+    env->nvic = nvic;
+    qdev_init_nofail(nvic);
+    sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
+                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
+    for (i = 0; i < 64; i++) {
+        pic[i] = qdev_get_gpio_in(nvic, i);
+    }
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    big_endian = 1;
+#else
+    big_endian = 0;
+#endif
+
+    if (!kernel_filename && !qtest_enabled() && !with_gdb) {
+        fprintf(stderr, "Guest image must be specified (using -kernel)\n");
+        exit(1);
+    }
+
+    /* Fill-in a minimalistic boot info, required for semihosting.  */
+    cortexm_binfo.kernel_cmdline = kernel_cmdline;
+    cortexm_binfo.kernel_filename = machine->kernel_cmdline;
+
+    env->boot_info = &cortexm_binfo;
+
+    if (kernel_filename) {
+        image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
+                              NULL, big_endian, ELF_MACHINE, 1);
+        if (image_size < 0) {
+            image_size = load_image_targphys(kernel_filename, 0, flash_size);
+            lowaddr = 0;
+        }
+        if (image_size < 0) {
+            error_report("Could not load kernel '%s'", kernel_filename);
+            exit(1);
+        }
+    }
+
+    /* Hack to map an additional page of ram at the top of the address
+     space.  This stops qemu complaining about executing code outside RAM
+     when returning from an exception.  */
+    memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000, &error_abort);
+    vmstate_register_ram_global(hack);
+    memory_region_add_subregion(system_memory, 0xfffff000, hack);
+
+    qemu_register_reset(cortexm_reset, cpu);
 
     /* Assume 8000000 Hz */
     /* TODO: compute according to board clock & pll settings */
@@ -66,6 +193,7 @@ qemu_irq *cortex_m_core_init(cortex_m_core_info *cm_info, MachineState *machine)
     return pic;
 }
 
+
 /* Cortex-M0 initialisation routine.  */
 qemu_irq *cortex_m0_core_init(cortex_m_core_info *cm_info, MachineState *machine)
 {
@@ -111,5 +239,12 @@ qemu_irq *cortex_m7_core_init(cortex_m_core_info *cm_info, MachineState *machine
     return cortex_m_core_init(cm_info, machine);
 }
 
+static void cortexm_reset(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+
+    cpu_reset(CPU(cpu));
+}
+
 /* -------------------------------------------------------------------------- */
 

include/hw/arm/cortexm.h

@@ -44,7 +44,4 @@ qemu_irq *cortex_m3_core_init(cortex_m_core_info *cm_info, MachineState *machine
 qemu_irq *cortex_m4_core_init(cortex_m_core_info *cm_info, MachineState *machine);
 qemu_irq *cortex_m7_core_init(cortex_m_core_info *cm_info, MachineState *machine);
 
-qemu_irq *cortexm_armv7m_init(MemoryRegion *system_memory, int flash_size_kb,
-                              int sram_size_kb, MachineState *machine);
-
 #endif /* HW_ARM_CORTEXM_H */

include/sysemu/sysemu.h

@@ -2,6 +2,7 @@
 #define SYSEMU_H
 /* Misc. things related to the system emulator.  */
 
+#include "config-host.h"
 #include "qemu/typedefs.h"
 #include "qemu/option.h"
 #include "qemu/queue.h"
@@ -102,8 +103,9 @@ typedef enum DisplayType
 
 extern int autostart;
 
-// [ILG]
+#if defined(CONFIG_GNU_ARM_ECLIPSE)
 extern int with_gdb;
+#endif
 #if defined(CONFIG_VERBOSE)
 extern int verbosity_level;
 #endif