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  1. UPduino-Mecrisp-Ice-15kB UPduino-Mecrisp-Ice-15kB Public

    Mecrisp-Ice Forth running on 16bit j1a processor (iCE40UP5k based UPduino board) with full 15kB of bram and 48bit Floating Point Library.

    Verilog 18 3

  2. SpinalHDL SpinalHDL Public

    Forked from SpinalHDL/SpinalHDL

    Scala based HDL

    Scala

  3. VexRiscv VexRiscv Public

    Forked from SpinalHDL/VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    Assembly

  4. YosysHQ/picorv32 YosysHQ/picorv32 Public

    PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog 3.2k 767

  5. Risc-V-on-FPGA-experiments Risc-V-on-FPGA-experiments Public

    My naive experiments with RudoIV and picorv32

    C