Skip to content

Commit

Permalink
Merge pull request chipsalliance#3919 from alainmarcel/alainmarcel-pa…
Browse files Browse the repository at this point in the history 
…tch-1

unpacked struct member
  • Loading branch information
@alaindargelas
alaindargelas authored Oct 31, 2023
2 parents 343c5c9 + 0ab04dc commit af49551
Show file tree
Hide file tree
Showing 34 changed files with 1,868 additions and 175 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/non_vendored.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ jobs:
cmake -B build -DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_STANDARD=17 -DCMAKE_POSITION_INDEPENDENT_CODE=ON -DJSON_BuildTests=OFF . && cmake --build build && sudo cmake --install build
popd
git clone --depth 1 --branch v1.76 https://github.com/chipsalliance/UHDM.git
git clone --depth 1 --branch v1.77 https://github.com/chipsalliance/UHDM.git
pushd UHDM
cmake -B build -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DUHDM_USE_HOST_GTEST=ON -DUHDM_USE_HOST_CAPNP=ON . && cmake --build build && sudo cmake --install build
popd
Expand Down
2 changes: 1 addition & 1 deletion .gitmodules
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
[submodule "third_party/UHDM"]
path = third_party/UHDM
url = https://github.com/chipsalliance/UHDM.git
branch = v1.76
branch = v1.77
[submodule "third_party/antlr4"]
path = third_party/antlr4
url = https://github.com/antlr/antlr4.git
Expand Down
2 changes: 1 addition & 1 deletion CMakeLists.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 3.20 FATAL_ERROR)
# Version changes whenever some new features accumulated, or the
# grammar or the cache format changes to make sure caches
# are invalidated.
project(SURELOG VERSION 1.76)
project(SURELOG VERSION 1.77)

# Detect build type, fallback to release and throw a warning if use didn't
# specify any
Expand Down
1 change: 1 addition & 0 deletions include/Surelog/ErrorReporting/ErrorDefinition.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -194,6 +194,7 @@ class ErrorDefinition {
COMP_SKIPPING_BLACKBOX_MODULE = 342,
COMP_SKIPPING_BLACKBOX_INSTANCE = 343,
COMP_ILLEGAL_DEFAULT_PORT_VALUE = 344,
COMP_UNPACKED_IN_PACKED = 345,
PY_PROCESSING_SOURCE_FILE = 400,
PY_NO_PYTHON_LISTENER_FOUND = 401,
ELAB_NO_MODULE_DEFINITION = 500,
Expand Down
29 changes: 29 additions & 0 deletions src/DesignCompile/CompileType.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1683,6 +1683,35 @@ UHDM::typespec* CompileHelper::compileTypespec(
reduce, nullptr, instance, false);
m->Default_value((expr*)ex);
}
if (Expression &&
(fC->Type(Expression) == VObjectType::paVariable_dimension)) {
NodeId Unpacked_dimension = fC->Child(Expression);
if (fC->Type(Unpacked_dimension) ==
VObjectType::paUnpacked_dimension) {
int32_t size;
VectorOfrange* ranges = compileRanges(
component, fC, Unpacked_dimension, compileDesign, reduce,
pstmt, instance, size, false);
array_typespec* pats = s.MakeArray_typespec();
ref_typespec* ref = s.MakeRef_typespec();
if (isPacked) {
ErrorContainer* errors =
compileDesign->getCompiler()->getErrorContainer();
SymbolTable* symbols =
compileDesign->getCompiler()->getSymbolTable();
Location loc1(
fC->getFileId(), fC->Line(Unpacked_dimension),
fC->Column(Unpacked_dimension),
symbols->registerSymbol(fC->SymName(member_name)));
Error err(ErrorDefinition::COMP_UNPACKED_IN_PACKED, loc1);
errors->addError(err);
}
pats->Elem_typespec(ref);
ref->Actual_typespec(m->Typespec()->Actual_typespec());
m->Typespec()->Actual_typespec(pats);
pats->Ranges(ranges);
}
}
if (component && member_ts &&
(member_ts->UhdmType() == uhdmunsupported_typespec)) {
component->needLateTypedefBinding(m);
Expand Down
2 changes: 2 additions & 0 deletions src/ErrorReporting/ErrorDefinition.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -356,6 +356,8 @@ bool ErrorDefinition::init() {
"Skipping blackboxed instance \"%s\"");
rec(COMP_ILLEGAL_DEFAULT_PORT_VALUE, ERROR, COMP,
"Illegal default value for port \"%s\"");
rec(COMP_UNPACKED_IN_PACKED, ERROR, COMP,
"Illegal unpacked member in packed struct \"%s\"");
rec(PY_PROCESSING_SOURCE_FILE, INFO, PYTH, "Processing source file \"%s\"");
rec(PY_NO_PYTHON_LISTENER_FOUND, FATAL, PYTH,
"No Python listener found (slSV3_1aPythonListener.py)");
Expand Down
55 changes: 44 additions & 11 deletions tests/CastTypespec/CastTypespec.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -724,15 +724,15 @@ AST_DEBUG_END
[INF:UH0706] Creating UHDM Model...
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
always 1
array_typespec 1
array_typespec 2
array_var 1
assign_stmt 1
assignment 2
begin 2
class_defn 8
class_typespec 4
class_var 3
constant 73
constant 76
cont_assign 1
design 1
enum_const 5
Expand All @@ -750,13 +750,13 @@ logic_net 9
logic_var 1
module_inst 9
named_begin 1
operation 26
operation 27
package 4
param_assign 30
parameter 30
range 2
range 3
ref_obj 20
ref_typespec 99
ref_typespec 100
string_typespec 2
struct_typespec 3
struct_var 2
Expand All @@ -768,15 +768,15 @@ typespec_member 8
[INF:UH0707] Elaborating UHDM...
=== UHDM Object Stats Begin (Elaborated Model) ===
always 2
array_typespec 1
array_typespec 2
array_var 2
assign_stmt 1
assignment 4
begin 4
class_defn 8
class_typespec 4
class_var 3
constant 73
constant 76
cont_assign 2
design 1
enum_const 10
Expand All @@ -794,13 +794,13 @@ logic_net 9
logic_var 1
module_inst 9
named_begin 2
operation 36
operation 37
package 4
param_assign 30
parameter 30
range 2
range 3
ref_obj 30
ref_typespec 108
ref_typespec 109
string_typespec 2
struct_typespec 3
struct_var 4
Expand Down Expand Up @@ -2016,7 +2016,7 @@ design: (work@tlul_adapter_host)
\_typespec_member: (b), line:27:27, endln:27:31
|vpiFullName:[email protected]_t.b
|vpiActual:
\_int_typespec: , line:27:21, endln:27:24
\_array_typespec:
|vpiRefFile:${SURELOG_DIR}/tests/CastTypespec/dut.sv
|vpiRefLineNo:27
|vpiRefColumnNo:21
Expand Down Expand Up @@ -2764,6 +2764,39 @@ design: (work@tlul_adapter_host)
|vpiParent:
\_typespec_member: (a), line:27:25, endln:27:26
|vpiSigned:1
\_array_typespec:
|vpiRange:
\_range: , line:27:29, endln:27:30
|vpiLeftRange:
\_constant:
|vpiParent:
\_range: , line:27:29, endln:27:30
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiRightRange:
\_operation: , line:27:29, endln:27:30
|vpiParent:
\_range: , line:27:29, endln:27:30
|vpiOpType:11
|vpiOperand:
\_constant: , line:27:29, endln:27:30
|vpiParent:
\_operation: , line:27:29, endln:27:30
|vpiDecompile:4
|vpiSize:64
|UINT:4
|vpiConstType:9
|vpiOperand:
\_constant:
|vpiSize:64
|INT:1
|vpiConstType:7
|vpiElemTypespec:
\_ref_typespec:
|vpiActual:
\_int_typespec: , line:27:21, endln:27:24
\_int_typespec: , line:27:21, endln:27:24
|vpiParent:
\_typespec_member: (b), line:27:27, endln:27:31
Expand Down
Loading

0 comments on commit af49551

Please sign in to comment.