Platform/Intel: Force PE/COFF sections 4KB aligned

Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table. Signed-off-by: Jiaxin Wu <[email protected]>
hsuc1x · Sep 18, 2024 · bd842b1 · bd842b1
1 parent 2e502d3
commit bd842b1
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOption.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOption.dsc
@@ -76,3 +76,7 @@
 #[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
 #  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
 #  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+[BuildOptions.common.EDKII.MM_CORE_STANDALONE, BuildOptions.common.EDKII.MM_STANDALONE]
+  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 /FILEALIGN:4096
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 /FILEALIGN:4096