v0.19: Added export to Verilog

- Added a tabbed pane to the attributes dialog to make it more beginner friendly.
- Added support for asynchronous sequential circuits such as the Muller-pipeline.
  Take a look at the new asynchronous examples for illustration.
- Added export to Verilog. Special thanks to Ivan de Jesus Deras Tabora, who has
  implemented the Verilog code generator and all the necessary Verilog templates!
- All examples are translated to english.
- A "test all" function has been added to start all tests in all circuits in
  the current folder.
- Very basic support for custom shapes added.
  You must manually edit the *.dig file to add a custom shape to a circuit, so
  this is only an option for advanced users.
- It is possible to use the 74xx chips with a more schematic shape, making it
  easier to build a circuit.
- Breaking changes:
  - Added an enable input to the terminal component.
  - Added a clock input to the keyboard component.
  - In your own DIL chips, you must correct the width attribute.
    The new value can be calculated as follows: new = (old*2)-1
- Bug fixes
  - Fixed a bug in the VHDL export concerning an invalid optimization of a
    std_logic_vector access.