updated the release notes

hneemann · Jun 11, 2018 · 814c703 · 814c703
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commit 814c703
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diff --git a/distribution/ReleaseNotes.txt b/distribution/ReleaseNotes.txt
@@ -4,6 +4,8 @@ HEAD, planned as v0.19
 - Added a tabbed pane to the attributes dialog to make it more beginner friendly.
 - Added support for asynchronous sequential circuits such as the Muller-pipeline.
   Take a look at the new asynchronous examples for illustration.
+- Added export to Verilog. Special thanks to Ivan de Jesus Deras Tabora, who has
+  implemented the Verilog code generator and all the necessary Verilog templates!
 - All examples are translated to english.
 - A "test all" function has been added to start all tests in all circuits in
   the current folder.