feat: upgrade to Rust 2024

Cargo.toml

@@ -18,7 +18,7 @@ keywords = ["unikernel", "libos"]
 categories = ["os"]
 repository = "https://github.com/hermit-os/kernel"
 documentation = "https://hermit-os.github.io/kernel/hermit/"
-edition = "2021"
+edition = "2024"
 description = "A Rust-based library operating system"
 exclude = [
 	"/.github/*",

build.rs

@@ -4,7 +4,7 @@ use std::path::{Path, PathBuf};
 use std::process::Command;
 use std::{env, fs};
 
-use anyhow::{anyhow, Context, Result};
+use anyhow::{Context, Result, anyhow};
 use llvm_tools::LlvmTools;
 
 fn main() -> Result<()> {

hermit-builtins/Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "hermit-builtins"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 
 [dependencies]
 libm = "0.2"

hermit-macro/Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "hermit-macro"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 
 [lib]
 proc-macro = true

hermit-macro/src/system.rs

@@ -1,6 +1,6 @@
 use proc_macro2::{Ident, Span};
 use quote::quote;
-use syn::{parse_quote, Abi, Attribute, FnArg, Item, ItemFn, Pat, Result, Signature, Visibility};
+use syn::{Abi, Attribute, FnArg, Item, ItemFn, Pat, Result, Signature, Visibility, parse_quote};
 
 fn validate_vis(vis: &Visibility) -> Result<()> {
 	if !matches!(vis, Visibility::Public(_)) {

src/arch/aarch64/kernel/core_local.rs

@@ -8,8 +8,8 @@ use core::sync::atomic::Ordering;
 #[cfg(feature = "smp")]
 use hermit_sync::InterruptTicketMutex;
 
-use super::interrupts::{IrqStatistics, IRQ_COUNTERS};
 use super::CPU_ONLINE;
+use super::interrupts::{IRQ_COUNTERS, IrqStatistics};
 use crate::executor::task::AsyncTask;
 #[cfg(feature = "smp")]
 use crate::scheduler::SchedulerInput;

src/arch/aarch64/kernel/pci.rs

@@ -6,14 +6,14 @@ use bit_field::BitField;
 use hermit_dtb::Dtb;
 use memory_addresses::arch::aarch64::{PhysAddr, VirtAddr};
 use pci_types::{
-	Bar, CommandRegister, ConfigRegionAccess, InterruptLine, InterruptPin, PciAddress, PciHeader,
-	MAX_BARS,
+	Bar, CommandRegister, ConfigRegionAccess, InterruptLine, InterruptPin, MAX_BARS, PciAddress,
+	PciHeader,
 };
 
 use crate::arch::aarch64::kernel::interrupts::GIC;
 use crate::arch::aarch64::mm::paging::{self, BasePageSize, PageSize, PageTableEntryFlags};
 use crate::arch::aarch64::mm::virtualmem;
-use crate::drivers::pci::{PciDevice, PCI_DEVICES};
+use crate::drivers::pci::{PCI_DEVICES, PciDevice};
 use crate::env;
 
 const PCI_MAX_DEVICE_NUMBER: u8 = 32;
@@ -196,9 +196,7 @@ fn detect_interrupt(
 
 		trace!(
 			"Interrupt type {:#x}, number {:#x} flags {:#x}",
-			irq_type,
-			irq_number,
-			irq_flags
+			irq_type, irq_number, irq_flags
 		);
 
 		if high.get_bits(0..24) == addr {
@@ -250,7 +248,10 @@ pub fn init() {
 
 				let pci_address =
 					virtualmem::allocate_aligned(size.try_into().unwrap(), 0x1000_0000).unwrap();
-				info!("Mapping PCI Enhanced Configuration Space interface to virtual address {:p} (size {:#X})", pci_address, size);
+				info!(
+					"Mapping PCI Enhanced Configuration Space interface to virtual address {:p} (size {:#X})",
+					pci_address, size
+				);
 
 				let mut flags = PageTableEntryFlags::empty();
 				flags.device().writable().execute_disable();
@@ -292,12 +293,9 @@ pub fn init() {
 								if let Some(bar) = dev.get_bar(i.try_into().unwrap()) {
 									match bar {
 										Bar::Io { .. } => {
-											dev.set_bar(
-												i.try_into().unwrap(),
-												Bar::Io {
-													port: io_start.try_into().unwrap(),
-												},
-											);
+											dev.set_bar(i.try_into().unwrap(), Bar::Io {
+												port: io_start.try_into().unwrap(),
+											});
 											io_start += 0x20;
 											cmd |= CommandRegister::IO_ENABLE
 												| CommandRegister::BUS_MASTER_ENABLE;
@@ -313,14 +311,11 @@ pub fn init() {
 											size,
 											prefetchable,
 										} => {
-											dev.set_bar(
-												i.try_into().unwrap(),
-												Bar::Memory64 {
-													address: mem64_start,
-													size,
-													prefetchable,
-												},
-											);
+											dev.set_bar(i.try_into().unwrap(), Bar::Memory64 {
+												address: mem64_start,
+												size,
+												prefetchable,
+											});
 											mem64_start += size;
 											cmd |= CommandRegister::MEMORY_ENABLE
 												| CommandRegister::BUS_MASTER_ENABLE;

src/arch/aarch64/kernel/processor.rs

@@ -1,9 +1,9 @@
 use core::arch::asm;
 use core::{fmt, str};
 
-use aarch64::regs::{Readable, CNTFRQ_EL0};
+use aarch64::regs::{CNTFRQ_EL0, Readable};
 use hermit_dtb::Dtb;
-use hermit_sync::{without_interrupts, Lazy};
+use hermit_sync::{Lazy, without_interrupts};
 
 use crate::env;
 

src/arch/aarch64/kernel/scheduler.rs

@@ -1,7 +1,7 @@
 //! Architecture dependent interface to initialize a task
 
 #[cfg(not(feature = "common-os"))]
-use alloc::alloc::{alloc_zeroed, Layout};
+use alloc::alloc::{Layout, alloc_zeroed};
 #[cfg(not(feature = "common-os"))]
 use alloc::boxed::Box;
 use core::arch::naked_asm;
@@ -13,14 +13,14 @@ use core::{mem, ptr};
 use align_address::Align;
 use memory_addresses::arch::aarch64::{PhysAddr, VirtAddr};
 
-use crate::arch::aarch64::kernel::core_local::core_scheduler;
 use crate::arch::aarch64::kernel::CURRENT_STACK_ADDRESS;
+use crate::arch::aarch64::kernel::core_local::core_scheduler;
 use crate::arch::aarch64::mm::paging::{BasePageSize, PageSize, PageTableEntryFlags};
 #[cfg(not(feature = "common-os"))]
 use crate::env;
-use crate::scheduler::task::{Task, TaskFrame};
 #[cfg(target_os = "none")]
 use crate::scheduler::PerCoreSchedulerExt;
+use crate::scheduler::task::{Task, TaskFrame};
 use crate::{DEFAULT_STACK_SIZE, KERNEL_STACK_SIZE};
 
 #[derive(Debug)]
@@ -297,15 +297,15 @@ impl TaskTLS {
 			let raw = ptr::slice_from_raw_parts_mut(data, block_len) as *mut TaskTLS;
 
 			let addr = (*raw).block.as_ptr().add(off).cast::<()>();
-			(*raw).dtv.as_mut_ptr().write(Box::new([
-				Dtv { counter: 1 },
-				Dtv {
+			(*raw)
+				.dtv
+				.as_mut_ptr()
+				.write(Box::new([Dtv { counter: 1 }, Dtv {
 					pointer: DtvPointer {
 						val: addr,
 						to_free: ptr::null(),
 					},
-				},
-			]));
+				}]));
 
 			Box::from_raw(raw)
 		};

src/arch/aarch64/kernel/start.rs

@@ -1,10 +1,10 @@
 use core::arch::{asm, naked_asm};
 
-use hermit_entry::boot_info::RawBootInfo;
 use hermit_entry::Entry;
+use hermit_entry::boot_info::RawBootInfo;
 
 use crate::arch::aarch64::kernel::scheduler::TaskStacks;
-use crate::{env, KERNEL_STACK_SIZE};
+use crate::{KERNEL_STACK_SIZE, env};
 
 unsafe extern "C" {
 	static vector_table: u8;

src/arch/aarch64/mm/paging.rs

@@ -10,7 +10,7 @@ use memory_addresses::{PhysAddr, VirtAddr};
 use crate::arch::aarch64::kernel::{get_base_address, get_image_size, get_ram_address, processor};
 use crate::arch::aarch64::mm::{physicalmem, virtualmem};
 use crate::env::is_uhyve;
-use crate::{mm, scheduler, KERNEL_STACK_SIZE};
+use crate::{KERNEL_STACK_SIZE, mm, scheduler};
 
 /// Pointer to the root page table (called "Level 0" in ARM terminology).
 /// Setting the upper bits to zero tells the MMU to use TTBR0 for the base address for the first table.
@@ -587,9 +587,7 @@ pub fn map<S: PageSize>(
 ) {
 	trace!(
 		"Mapping virtual address {:p} to physical address {:p} ({} pages)",
-		virtual_address,
-		physical_address,
-		count
+		virtual_address, physical_address, count
 	);
 
 	let range = get_page_range::<S>(virtual_address, count);
@@ -620,8 +618,7 @@ pub fn map_heap<S: PageSize>(virt_addr: VirtAddr, count: usize) -> Result<(), us
 pub fn unmap<S: PageSize>(virtual_address: VirtAddr, count: usize) {
 	trace!(
 		"Unmapping virtual address {:p} ({} pages)",
-		virtual_address,
-		count
+		virtual_address, count
 	);
 
 	let range = get_page_range::<S>(virtual_address, count);

src/arch/riscv64/kernel/interrupts.rs

@@ -8,11 +8,11 @@ use riscv::interrupt::{Exception, Interrupt, Trap};
 use riscv::register::{scause, sie, sip, sstatus, stval};
 use trapframe::TrapFrame;
 
+use crate::drivers::InterruptHandlerQueue;
 #[cfg(not(feature = "pci"))]
 use crate::drivers::mmio::get_interrupt_handlers;
 #[cfg(feature = "pci")]
 use crate::drivers::pci::get_interrupt_handlers;
-use crate::drivers::InterruptHandlerQueue;
 use crate::scheduler;
 
 /// base address of the PLIC, only one access at the same time is allowed

src/arch/riscv64/kernel/mod.rs

@@ -20,7 +20,7 @@ use fdt::Fdt;
 use memory_addresses::{PhysAddr, VirtAddr};
 use riscv::register::sstatus;
 
-use crate::arch::riscv64::kernel::core_local::{core_id, CoreLocal};
+use crate::arch::riscv64::kernel::core_local::{CoreLocal, core_id};
 pub use crate::arch::riscv64::kernel::devicetree::init_drivers;
 use crate::arch::riscv64::kernel::processor::lsb;
 use crate::arch::riscv64::mm::physicalmem;

src/arch/riscv64/kernel/processor.rs

@@ -4,7 +4,7 @@ use core::num::NonZeroU64;
 
 use riscv::register::{sie, sstatus, time};
 
-use crate::arch::riscv64::kernel::{get_timebase_freq, HARTS_AVAILABLE};
+use crate::arch::riscv64::kernel::{HARTS_AVAILABLE, get_timebase_freq};
 use crate::scheduler::CoreId;
 
 /// Current FPU state. Saved at context switch when changed

src/arch/riscv64/kernel/scheduler.rs

@@ -1,5 +1,5 @@
 #[cfg(not(feature = "common-os"))]
-use alloc::alloc::{alloc, dealloc, Layout};
+use alloc::alloc::{Layout, alloc, dealloc};
 #[cfg(not(feature = "common-os"))]
 use alloc::boxed::Box;
 #[cfg(not(feature = "common-os"))]
@@ -282,7 +282,7 @@ impl TaskTLS {
 		// Yes, it does, so we have to allocate TLS memory.
 		// Allocate enough space for the given size and one more variable of type usize, which holds the tls_pointer.
 		let tls_allocation_size = tls_size.align_up(32usize); // + mem::size_of::<usize>();
-														// We allocate in 128 byte granularity (= cache line size) to avoid false sharing
+		// We allocate in 128 byte granularity (= cache line size) to avoid false sharing
 		let memory_size = tls_allocation_size.align_up(128usize);
 		let layout =
 			Layout::from_size_align(memory_size, 128).expect("TLS has an invalid size / alignment");

src/arch/riscv64/kernel/start.rs

@@ -2,14 +2,14 @@ use core::arch::naked_asm;
 use core::sync::atomic::Ordering;
 
 use fdt::Fdt;
-use hermit_entry::boot_info::RawBootInfo;
 use hermit_entry::Entry;
+use hermit_entry::boot_info::RawBootInfo;
 
-use super::{get_dtb_ptr, CPU_ONLINE, CURRENT_BOOT_ID, HART_MASK, NUM_CPUS};
+use super::{CPU_ONLINE, CURRENT_BOOT_ID, HART_MASK, NUM_CPUS, get_dtb_ptr};
+use crate::arch::riscv64::kernel::CURRENT_STACK_ADDRESS;
 #[cfg(not(feature = "smp"))]
 use crate::arch::riscv64::kernel::processor;
-use crate::arch::riscv64::kernel::CURRENT_STACK_ADDRESS;
-use crate::{env, KERNEL_STACK_SIZE};
+use crate::{KERNEL_STACK_SIZE, env};
 
 //static mut BOOT_STACK: [u8; KERNEL_STACK_SIZE] = [0; KERNEL_STACK_SIZE];
 

src/arch/riscv64/mm/paging.rs

@@ -597,9 +597,7 @@ pub fn map<S: PageSize>(
 ) {
 	trace!(
 		"Mapping physical address {:#X} to virtual address {:#X} ({} pages)",
-		physical_address,
-		virtual_address,
-		count
+		physical_address, virtual_address, count
 	);
 
 	let range = get_page_range::<S>(virtual_address, count);
@@ -631,8 +629,7 @@ pub fn map_heap<S: PageSize>(virt_addr: VirtAddr, count: usize) -> Result<(), us
 pub fn unmap<S: PageSize>(virtual_address: VirtAddr, count: usize) {
 	trace!(
 		"Unmapping virtual address {:#X} ({} pages)",
-		virtual_address,
-		count
+		virtual_address, count
 	);
 
 	let range = get_page_range::<S>(virtual_address, count);
@@ -650,8 +647,7 @@ pub fn identity_map<S: PageSize>(memory: AddrRange<PhysAddr>) {
 
 	trace!(
 		"identity_map address {:#X} to address {:#X}",
-		first_page.virtual_address,
-		last_page.virtual_address,
+		first_page.virtual_address, last_page.virtual_address,
 	);
 
 	/* assert!(

src/arch/x86_64/kernel/acpi.rs

@@ -264,11 +264,7 @@ fn verify_checksum(start_address: usize, length: usize) -> Result<(), ()> {
 	let checksum = slice.iter().fold(0, |acc: u8, x| acc.wrapping_add(*x));
 
 	// This sum must equal to zero to be valid.
-	if checksum == 0 {
-		Ok(())
-	} else {
-		Err(())
-	}
+	if checksum == 0 { Ok(()) } else { Err(()) }
 }
 
 /// Tries to find the ACPI RSDP within the specified address range.

src/arch/x86_64/kernel/apic.rs

@@ -13,16 +13,16 @@ use align_address::Align;
 #[cfg(feature = "smp")]
 use arch::x86_64::kernel::core_local::*;
 use arch::x86_64::kernel::{interrupts, processor};
-use hermit_sync::{without_interrupts, OnceCell, SpinMutex};
+use hermit_sync::{OnceCell, SpinMutex, without_interrupts};
 use memory_addresses::{AddrRange, PhysAddr, VirtAddr};
 #[cfg(feature = "smp")]
 use x86::controlregs::*;
 use x86::msr::*;
 
 use super::interrupts::IDT;
+use crate::arch::x86_64::kernel::CURRENT_STACK_ADDRESS;
 #[cfg(feature = "acpi")]
 use crate::arch::x86_64::kernel::acpi;
-use crate::arch::x86_64::kernel::CURRENT_STACK_ADDRESS;
 use crate::arch::x86_64::mm::paging::{
 	BasePageSize, PageSize, PageTableEntryFlags, PageTableEntryFlagsExt,
 };
@@ -615,8 +615,8 @@ fn calibrate_timer() {
 		.set(calibrated_counter_value)
 		.unwrap();
 	debug!(
-			"Calibrated APIC Timer with a counter value of {calibrated_counter_value} for 1 microsecond",
-		);
+		"Calibrated APIC Timer with a counter value of {calibrated_counter_value} for 1 microsecond",
+	);
 }
 
 fn __set_oneshot_timer(wakeup_time: Option<u64>) {

src/arch/x86_64/kernel/core_local.rs

@@ -9,12 +9,12 @@ use core::{mem, ptr};
 
 #[cfg(feature = "smp")]
 use hermit_sync::InterruptTicketMutex;
+use x86_64::VirtAddr;
 use x86_64::registers::model_specific::GsBase;
 use x86_64::structures::tss::TaskStateSegment;
-use x86_64::VirtAddr;
 
-use super::interrupts::{IrqStatistics, IRQ_COUNTERS};
 use super::CPU_ONLINE;
+use super::interrupts::{IRQ_COUNTERS, IrqStatistics};
 use crate::executor::task::AsyncTask;
 #[cfg(feature = "smp")]
 use crate::scheduler::SchedulerInput;