Merge pull request #1535 from hermit-os/nightly-2025-01-01

chore: upgrade toolchain channel to `nightly-2025-01-01`

hermit-macro/src/system.rs

@@ -107,6 +107,7 @@ fn emit_func(mut func: ItemFn, sig: &ParsedSig) -> Result<ItemFn> {
 			_ => unreachable!(),
 		})
 		.collect::<Vec<_>>();
+	#[allow(clippy::literal_string_with_formatting_args)]
 	let input_format = input_idents
 		.iter()
 		.map(|ident| format!("{ident} = {{:?}}"))

rust-toolchain.toml

@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2024-12-15"
+channel = "nightly-2025-01-01"
 components = [
     "llvm-tools",
     "rust-src",

src/arch/aarch64/kernel/pci.rs

@@ -34,9 +34,9 @@ impl PciConfigRegion {
 	#[inline]
 	fn addr_from_offset(&self, pci_addr: PciAddress, offset: u16) -> usize {
 		assert!(offset & 0xf000 == 0, "Invalid offset");
-		(u64::from(pci_addr.bus()) << 20
-			| u64::from(pci_addr.device()) << 15
-			| u64::from(pci_addr.function()) << 12
+		((u64::from(pci_addr.bus()) << 20)
+			| (u64::from(pci_addr.device()) << 15)
+			| (u64::from(pci_addr.function()) << 12)
 			| (u64::from(offset) & 0xfff)
 			| self.0.as_u64()) as usize
 	}
@@ -127,7 +127,7 @@ fn detect_interrupt(
 	dtb: &Dtb<'_>,
 	parts: &[&str],
 ) -> Option<(InterruptPin, InterruptLine)> {
-	let addr = bus << 16 | dev << 11;
+	let addr = (bus << 16) | (dev << 11);
 	if addr == 0 {
 		// assume PCI bridge => no configuration required
 		return None;

src/arch/aarch64/kernel/processor.rs

@@ -180,7 +180,7 @@ pub fn configure() {
 	unsafe {
 		// TODO: Setting PMUSERENR_EL0 is probably not required, but find out about that
 		// when reading PMCCNTR_EL0 works at all.
-		let pmuserenr_el0: u64 = 1 << 0 | 1 << 2 | 1 << 3;
+		let pmuserenr_el0: u64 = (1 << 0) | (1 << 2) | (1 << 3);
 		asm!(
 			"msr pmuserenr_el0, {}",
 			in(reg) pmuserenr_el0,
@@ -207,7 +207,7 @@ pub fn configure() {
 			"PMCR_EL0 (has RES1 bits and therefore mustn't be zero): {:#X}",
 			pmcr_el0
 		);
-		pmcr_el0 |= 1 << 0 | 1 << 2 | 1 << 6;
+		pmcr_el0 |= (1 << 0) | (1 << 2) | (1 << 6);
 		asm!(
 			"msr pmcr_el0, {}",
 			in(reg) pmcr_el0,

src/arch/aarch64/mm/paging.rs

@@ -49,7 +49,7 @@ bitflags! {
 		const DEVICE_GRE = 1 << 3;
 
 		/// Set if this entry points to normal memory (non-cacheable)
-		const NORMAL_NC = 1 << 3 | 1 << 2;
+		const NORMAL_NC = (1 << 3) | (1 << 2);
 
 		/// Set if this entry points to normal memory (cacheable)
 		const NORMAL = 1 << 4;
@@ -58,7 +58,7 @@ bitflags! {
 		const READ_ONLY = 1 << 7;
 
 		/// Set if this entry shall be shared between all cores of the system.
-		const INNER_SHAREABLE = 1 << 8 | 1 << 9;
+		const INNER_SHAREABLE = (1 << 8) | (1 << 9);
 
 		/// Set if software has accessed this entry (for memory access or address translation).
 		const ACCESSED = 1 << 10;
@@ -272,7 +272,7 @@ impl<S: PageSize> Page<S> {
 	/// Returns the index of this page in the table given by L.
 	fn table_index<L: PageTableLevel>(&self) -> usize {
 		assert!(L::LEVEL <= S::MAP_LEVEL);
-		self.virtual_address.as_usize() >> PAGE_BITS >> ((3 - L::LEVEL) * PAGE_MAP_BITS)
+		(self.virtual_address.as_usize() >> PAGE_BITS >> ((3 - L::LEVEL) * PAGE_MAP_BITS))
 			& PAGE_MAP_MASK
 	}
 }

src/arch/riscv64/mm/paging.rs

@@ -55,7 +55,7 @@ bitflags! {
 		const DIRTY = 1 << 7;
 
 		/// The RSW field is reserved for use by supervisor
-		const RSW  = 1 << 8 | 1 << 9;
+		const RSW  = (1 << 8) | (1 << 9);
 	}
 }
 
@@ -259,7 +259,7 @@ impl<S: PageSize> Page<S> {
 	/// Returns the index of this page in the table given by L.
 	fn table_index<L: PageTableLevel>(self) -> usize {
 		assert!(L::LEVEL >= S::MAP_LEVEL);
-		self.virtual_address.as_usize() >> PAGE_BITS >> (L::LEVEL * PAGE_MAP_BITS) & PAGE_MAP_MASK
+		(self.virtual_address.as_usize() >> PAGE_BITS >> (L::LEVEL * PAGE_MAP_BITS)) & PAGE_MAP_MASK
 	}
 }
 
@@ -682,12 +682,12 @@ pub fn init_page_tables() {
 		.unwrap(),
 	);
 	// FIXME: This is not sound, since we are ignoring races with the hardware.
-	satp::write(0x8 << 60 | (ROOT_PAGETABLE.data_ptr().addr() >> 12));
+	satp::write((0x8 << 60) | (ROOT_PAGETABLE.data_ptr().addr() >> 12));
 }
 
 #[cfg(feature = "smp")]
 pub fn init_application_processor() {
 	trace!("Identity map the physical memory using HugePages");
 	// FIXME: This is not sound, since we are ignoring races with the hardware.
-	satp::write(0x8 << 60 | (ROOT_PAGETABLE.data_ptr().addr() >> 12));
+	satp::write((0x8 << 60) | (ROOT_PAGETABLE.data_ptr().addr() >> 12));
 }

src/arch/x86_64/kernel/pci.rs

@@ -24,9 +24,9 @@ impl ConfigRegionAccess for PciConfigRegion {
 	#[inline]
 	unsafe fn read(&self, pci_addr: PciAddress, register: u16) -> u32 {
 		let address = PCI_CONFIG_ADDRESS_ENABLE
-			| u32::from(pci_addr.bus()) << 16
-			| u32::from(pci_addr.device()) << 11
-			| u32::from(pci_addr.function()) << 8
+			| (u32::from(pci_addr.bus()) << 16)
+			| (u32::from(pci_addr.device()) << 11)
+			| (u32::from(pci_addr.function()) << 8)
 			| u32::from(register);
 		unsafe {
 			outl(PCI_CONFIG_ADDRESS_PORT, address);
@@ -37,9 +37,9 @@ impl ConfigRegionAccess for PciConfigRegion {
 	#[inline]
 	unsafe fn write(&self, pci_addr: PciAddress, register: u16, value: u32) {
 		let address = PCI_CONFIG_ADDRESS_ENABLE
-			| u32::from(pci_addr.bus()) << 16
-			| u32::from(pci_addr.device()) << 11
-			| u32::from(pci_addr.function()) << 8
+			| (u32::from(pci_addr.bus()) << 16)
+			| (u32::from(pci_addr.device()) << 11)
+			| (u32::from(pci_addr.function()) << 8)
 			| u32::from(register);
 		unsafe {
 			outl(PCI_CONFIG_ADDRESS_PORT, address);

src/arch/x86_64/kernel/pic.rs

@@ -104,7 +104,7 @@ fn edit_mask(int_no: u8, insert: bool) {
 		let mask = inb(port);
 
 		if insert {
-			outb(port, mask | 1 << (int_no - offset));
+			outb(port, mask | (1 << (int_no - offset)));
 		} else {
 			outb(port, mask & !(1 << (int_no - offset)));
 		}

src/drivers/pci.rs

@@ -102,7 +102,7 @@ impl<T: ConfigRegionAccess> PciDevice<T> {
 				prefetchable,
 			} => {
 				if prefetchable {
-					(address | 1 << 3) as usize
+					(address | (1 << 3)) as usize
 				} else {
 					address as usize
 				}
@@ -113,9 +113,9 @@ impl<T: ConfigRegionAccess> PciDevice<T> {
 				prefetchable,
 			} => {
 				if prefetchable {
-					(address | 2 << 1 | 1 << 3) as usize
+					(address | (2 << 1) | (1 << 3)) as usize
 				} else {
-					(address | 2 << 1) as usize
+					(address | (2 << 1)) as usize
 				}
 			}
 		};

src/syscalls/interfaces/mod.rs

@@ -16,7 +16,7 @@ pub trait SyscallInterface: Send + Sync {
 	fn get_application_parameters(&self) -> (i32, *const *const u8, *const *const u8) {
 		let mut argv = Vec::new();
 
-		let name = Box::leak(Box::new("{name}\0")).as_ptr();
+		let name = Box::leak(Box::new("bin\0")).as_ptr();
 		argv.push(name);
 
 		let args = env::args();