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pw_clock_tree_mcuxpresso: Configure ClkIn as source for osc_clk
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This change automatically configures the ClkIn clock
source as input for the SYSOSCBYPASS clock selector
to generate the osc_clk signal when enabled. If disabled
the SYSOSCBYPASS clock selector will be clock gated.

Bug: 331672574
Change-Id: I2c616daa5e6247e1fac80fc7b7914b35254e8b95
Reviewed-on: https://pigweed-review.googlesource.com/c/pigweed/pigweed/+/214234
Presubmit-Verified: CQ Bot Account <[email protected]>
Lint: Lint 🤖 <[email protected]>
Commit-Queue: Christoph Klee <[email protected]>
Reviewed-by: Austin Foxley <[email protected]>
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Christoph Klee authored and CQ Bot Account committed Jun 5, 2024
1 parent 1ffc0b7 commit a4f3e67
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Showing 2 changed files with 11 additions and 2 deletions.
2 changes: 1 addition & 1 deletion pw_clock_tree_mcuxpresso/docs.rst
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ that can be directly instantiated:
* 32 kHz RTC Oscillator
* Low-power Oscillator
* Master Clock
* External Clock Input
* External Clock Input as clock source for SYSOSCBYPASS clock selector to generate OSC_CLK
* Fractional Rate Generator (FRG) for Flexcomm Interfaces
* Clock Source Selector
* Clock Divider
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,8 @@ using ClockMcuxpressoMclkBlocking = ClockMcuxpressoMclk<ElementBlocking>;
using ClockMcuxpressoMclkNonBlocking =
ClockMcuxpressoMclk<ElementNonBlockingCannotFail>;

/// Class template implementing the CLK IN pin clock source.
/// Class template implementing the CLK IN pin clock source and selecting
/// it as an input source for OSC Clock source.
///
/// Template argument `ElementType` can be of class `ElementBlocking` or
/// `ElementNonBlockingCannotFail`.
Expand All @@ -118,12 +119,20 @@ class ClockMcuxpressoClkIn final : public DependentElement<ElementType> {
pw::Status DoEnable() final {
CLOCK_SetClkinFreq(
frequency_); /*!< Sets CLK_IN pin clock frequency in Hz */

// OSC clock source selector ClkIn.
const uint8_t kCLOCK_OscClkIn = CLKCTL0_SYSOSCBYPASS_SEL(1);
CLKCTL0->SYSOSCBYPASS = kCLOCK_OscClkIn;
return pw::OkStatus();
}

/// Set CLK IN clock frequency to 0 Hz.
pw::Status DoDisable() final {
CLOCK_SetClkinFreq(0); /*!< Sets CLK_IN pin clock frequency in Hz */

// OSC clock source selector None, which gates output to reduce power.
const uint8_t kCLOCK_OscNone = CLKCTL0_SYSOSCBYPASS_SEL(7);
CLKCTL0->SYSOSCBYPASS = kCLOCK_OscNone;
return pw::OkStatus();
}

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