pw_cpu_exception_cortex_m: Fix checks for ARMv8

Check for _PW_ARCH_ARM_V8M_MAINLINE or _PW_ARCH_ARM_V8_1M_MAINLINE as some cortex M cores set one but not the other. Change-Id: I23e0d6fab2563f82dc9e3b8ece75b568da72b4cf Reviewed-on: https://pigweed-review.googlesource.com/c/pigweed/pigweed/+/210272 Lint: Lint 🤖 <[email protected]> Commit-Queue: Carlos Chinchilla <[email protected]> Reviewed-by: Ewout van Bekkum <[email protected]> Reviewed-by: Armando Montanez <[email protected]>
google · May 21, 2024 · 4d84714 · 4d84714
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commit 4d84714
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Showing 6 changed files with 25 additions and 25 deletions.
diff --git a/pw_cpu_exception_cortex_m/entry.cc b/pw_cpu_exception_cortex_m/entry.cc
@@ -44,9 +44,9 @@ bool FpuStateWasPushed(const pw_cpu_exception_State& cpu_state) {
 void CloneBaseRegistersFromPsp(pw_cpu_exception_State* cpu_state) {
   // If CPU succeeded in pushing context to PSP, copy it to the MSP.
   if (!(cpu_state->extended.cfsr & kCfsrStkerrMask) &&
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
       !(cpu_state->extended.cfsr & kCfsrStkofMask) &&
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
       !(cpu_state->extended.cfsr & kCfsrMstkerrMask)) {
     // TODO(amontanez): {r0-r3,r12} are captured in pw_cpu_exception_Entry(),
     //                  so this only really needs to copy pc, lr, and psr. Could
@@ -76,9 +76,9 @@ void RestoreBaseRegistersToPsp(pw_cpu_exception_State* cpu_state) {
   // continue. Otherwise, don't attempt as we'll likely end up in an escalated
   // hard fault.
   if (!(cpu_state->extended.cfsr & kCfsrStkerrMask) &&
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
       !(cpu_state->extended.cfsr & kCfsrStkofMask) &&
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
       !(cpu_state->extended.cfsr & kCfsrMstkerrMask)) {
     std::memcpy(reinterpret_cast<void*>(cpu_state->extended.psp),
                 &cpu_state->base,
@@ -110,9 +110,9 @@ uint32_t CalculatePspDelta(const pw_cpu_exception_State& cpu_state) {
   // need to be shifted.
   if (!ProcessStackActive(cpu_state) ||
       (cpu_state.extended.cfsr & kCfsrStkerrMask) ||
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
       (cpu_state.extended.cfsr & kCfsrStkofMask) ||
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
       (cpu_state.extended.cfsr & kCfsrMstkerrMask)) {
     return 0;
   }

diff --git a/pw_cpu_exception_cortex_m/proto_dump.cc b/pw_cpu_exception_cortex_m/proto_dump.cc
@@ -42,10 +42,10 @@ Status DumpCpuStateProto(protobuf::StreamEncoder& dest,
   state_encoder.WritePsp(extended.psp).IgnoreError();
   state_encoder.WriteExcReturn(extended.exc_return).IgnoreError();
   state_encoder.WriteCfsr(extended.cfsr).IgnoreError();
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   state_encoder.WriteMsplim(extended.msplim).IgnoreError();
   state_encoder.WritePsplim(extended.psplim).IgnoreError();
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   state_encoder.WriteMmfar(extended.mmfar).IgnoreError();
   state_encoder.WriteBfar(extended.bfar).IgnoreError();
   state_encoder.WriteIcsr(extended.icsr).IgnoreError();

diff --git a/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/cpu_state.h b/pw_cpu_exception_cortex_m/public/pw_cpu_exception_cortex_m/cpu_state.h
@@ -93,10 +93,10 @@ struct ExtraRegisters {
   uint32_t msp;
   uint32_t psp;
   uint32_t control;
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   uint32_t msplim;
   uint32_t psplim;
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   // General purpose registers.
   uint32_t r4;
   uint32_t r5;
@@ -108,11 +108,11 @@ struct ExtraRegisters {
   uint32_t r11;
 };
 static_assert(sizeof(ExtraRegisters) ==
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
                   (sizeof(uint32_t) * 20),
-#else   // !_PW_ARCH_ARM_V8M_MAINLINE
+#else   // !_PW_ARCH_ARM_V8M_MAINLINE && ! _PW_ARCH_ARM_V8_1M_MAINLINE
                   (sizeof(uint32_t) * 18),
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
               "There's unexpected padding.");
 
 }  // namespace pw::cpu_exception::cortex_m

diff --git a/pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_private/cortex_m_constants.h b/pw_cpu_exception_cortex_m/pw_cpu_exception_cortex_m_private/cortex_m_constants.h
@@ -76,18 +76,18 @@ constexpr uint32_t kCfsrUndefinstrMask = (kCfsrUsageFaultStart << 0);
 constexpr uint32_t kCfsrInvstateMask = (kCfsrUsageFaultStart << 1);
 constexpr uint32_t kCfsrInvpcMask = (kCfsrUsageFaultStart << 2);
 constexpr uint32_t kCfsrNocpMask = (kCfsrUsageFaultStart << 3);
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
 constexpr uint32_t kCfsrStkofMask = (kCfsrUsageFaultStart << 4);
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
 constexpr uint32_t kCfsrUnalignedMask = (kCfsrUsageFaultStart << 8);
 constexpr uint32_t kCfsrDivbyzeroMask = (kCfsrUsageFaultStart << 9);
 // Mask for all supported usage error flags i.e. bits that indicate a specific
 // error.
 constexpr uint32_t kCfsrUsageAllErrorsMask =
     kCfsrUndefinstrMask | kCfsrInvstateMask | kCfsrInvpcMask | kCfsrNocpMask |
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
     kCfsrStkofMask |
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
     kCfsrUnalignedMask | kCfsrDivbyzeroMask;
 
 // Bit masks for an exception return value. (ARMv7-M Section B1.5.8)

diff --git a/pw_cpu_exception_cortex_m/support.cc b/pw_cpu_exception_cortex_m/support.cc
@@ -55,10 +55,10 @@ void ToString(const pw_cpu_exception_State& cpu_state, const span<char>& dest) {
   _PW_FORMAT_REGISTER(extended, msp);
   _PW_FORMAT_REGISTER(extended, psp);
   _PW_FORMAT_REGISTER(extended, exc_return);
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   _PW_FORMAT_REGISTER(extended, msplim);
   _PW_FORMAT_REGISTER(extended, psplim);
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   _PW_FORMAT_REGISTER(extended, cfsr);
   _PW_FORMAT_REGISTER(extended, mmfar);
   _PW_FORMAT_REGISTER(extended, bfar);
@@ -110,10 +110,10 @@ void LogCpuState(const pw_cpu_exception_State& cpu_state) {
   _PW_LOG_REGISTER(extended, msp);
   _PW_LOG_REGISTER(extended, psp);
   _PW_LOG_REGISTER(extended, exc_return);
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   _PW_LOG_REGISTER(extended, msplim);
   _PW_LOG_REGISTER(extended, psplim);
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   _PW_LOG_REGISTER(extended, cfsr);
   _PW_LOG_REGISTER(extended, mmfar);
   _PW_LOG_REGISTER(extended, bfar);

diff --git a/pw_cpu_exception_cortex_m/util.cc b/pw_cpu_exception_cortex_m/util.cc
@@ -96,11 +96,11 @@ namespace {
   if (cfsr & kCfsrDivbyzeroMask) {
     PW_LOG_ERROR("  DIVBYZERO: Division by zero");
   }
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   if (cfsr & kCfsrStkofMask) {
     PW_LOG_ERROR("  STKOF: Stack overflowed");
   }
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
 }
 
 }  // namespace
@@ -113,15 +113,15 @@ void LogExceptionAnalysis(const pw_cpu_exception_State& cpu_state) {
   if (cpu_state.extended.hfsr & kHfsrForcedMask) {
     PW_LOG_CRITICAL("Encountered a nested CPU fault (See active CFSR fields)");
   }
-#if _PW_ARCH_ARM_V8M_MAINLINE
+#if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   if (cpu_state.extended.cfsr & kCfsrStkofMask) {
     if (ProcessStackActive(cpu_state)) {
       PW_LOG_CRITICAL("Encountered process stack overflow (psp)");
     } else {
       PW_LOG_CRITICAL("Encountered main stack overflow (msp)");
     }
   }
-#endif  // _PW_ARCH_ARM_V8M_MAINLINE
+#endif  // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE
   if (cpu_state.extended.cfsr & kCfsrMemFaultMask) {
     if (cpu_state.extended.cfsr & kCfsrMmarvalidMask) {
       PW_LOG_CRITICAL(