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Migrate TODOs to new issues, remove stale TODOs #375

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Jan 16, 2024
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Migrate TODOs to new issues, remove stale TODOs #375

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2 changes: 0 additions & 2 deletions include/Dialect/BGV/IR/BGVOps.td
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Expand Up @@ -14,8 +14,6 @@ def SameOperandsAndResultRings: NativeOpTrait<"SameOperandsAndResultRings"> {
class BGV_Op<string mnemonic, list<Trait> traits = []> :
Op<BGV_Dialect, mnemonic, traits> {

// See https://mlir.llvm.org/docs/DefiningDialects/Operations/#declarative-assembly-format
// TODO(#106): Simplify this format by adding type constraints.
let assemblyFormat = [{
`(` operands `)` attr-dict `:` `(` type(operands) `)` `->` type(results)
}];
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3 changes: 0 additions & 3 deletions lib/Target/TfheRust/TfheRustEmitter.cpp
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Expand Up @@ -33,9 +33,6 @@ namespace mlir {
namespace heir {
namespace tfhe_rust {

// TODO(#230): Have a separate pass that topo-sorts the gate ops into levels,
// and use scf.parallel_for to represent them.

void registerToTfheRustTranslation() {
TranslateFromMLIRRegistration reg(
"emit-tfhe-rust",
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1 change: 0 additions & 1 deletion lib/Transforms/YosysOptimizer/RTLILImporter.cpp
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Expand Up @@ -145,7 +145,6 @@ func::FuncOp RTLILImporter::importModule(
}

// Build function.
// TODO(#111): Pass in data to fix function location.
FunctionType funcType = builder.getFunctionType(argTypes, retTypes);
auto function = func::FuncOp::create(
builder.getUnknownLoc(), module->name.str().replace(0, 1, ""), funcType);
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2 changes: 1 addition & 1 deletion lib/Transforms/YosysOptimizer/YosysOptimizer.cpp
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Expand Up @@ -208,7 +208,7 @@ LogicalResult runOnGenericOp(MLIRContext *context, secret::GenericOp op,

// Translate function to Verilog. Translation will fail if the func contains
// unsupported operations.
// TODO(#111): Directly convert MLIR to Yosys' AST instead of using Verilog.
// TODO(#374): Directly convert MLIR to Yosys' AST instead of using Verilog.
//
// After that is done, it might make sense to rewrite this as a
// RewritePattern, which only runs if the body does not contain any comb ops,
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