add rtlil to mlir importer

Signed-off-by: Asra Ali <[email protected]>

WORKSPACE

@@ -154,6 +154,8 @@ hedron_compile_commands_setup()
 # install dependencies for yosys/ABC circuit optimizers
 http_archive(
     name = "rules_hdl",
+    patch_args = ["-p1"],
+    patches = ["//bazel:yosys.patch"],
     # Commit on 2023-06-13, current as of 2023-06-13.
     sha256 = "21307b0c14a036f1b4879c8f1d4d50a115053eb87c428307d4d6569c3e7ba859",
     strip_prefix = "bazel_rules_hdl-e6540a5bccbfb124aec0b19deaa9cf855781b3a5",

bazel/yosys.patch

@@ -0,0 +1,13 @@
+diff --git a/dependency_support/at_clifford_yosys/bundled.BUILD.bazel b/dependency_support/at_clifford_yosys/bundled.BUILD.bazel
+--- a/dependency_support/at_clifford_yosys/bundled.BUILD.bazel
++++ b/dependency_support/at_clifford_yosys/bundled.BUILD.bazel
+@@ -256,8 +256,9 @@
+     ]
+   ) + [
+     ":common_techlibs"
+   ],
++  visibility = ["//visibility:public"],
+ )
+
+ yosys_syntax_check(
+     name = "testing_yosys_syntax_check_build_rule",

include/Transforms/YosysOptimizer/BUILD

@@ -0,0 +1,35 @@
+load("@llvm-project//mlir:tblgen.bzl", "gentbl_cc_library")
+
+package(
+    default_applicable_licenses = ["@heir//:license"],
+    default_visibility = ["//visibility:public"],
+)
+
+exports_files(
+    [
+        "YosysOptimizer.h",
+    ],
+)
+
+gentbl_cc_library(
+    name = "pass_inc_gen",
+    tbl_outs = [
+        (
+            [
+                "-gen-pass-decls",
+                "-name=YosysOptimizer",
+            ],
+            "YosysOptimizer.h.inc",
+        ),
+        (
+            ["-gen-pass-doc"],
+            "YosysOptimizer.md",
+        ),
+    ],
+    tblgen = "@llvm-project//mlir:mlir-tblgen",
+    td_file = "YosysOptimizer.td",
+    deps = [
+        "@llvm-project//mlir:OpBaseTdFiles",
+        "@llvm-project//mlir:PassBaseTdFiles",
+    ],
+)

include/Transforms/YosysOptimizer/YosysOptimizer.h

@@ -0,0 +1,20 @@
+#ifndef INCLUDE_TRANSFORMS_YOSYSOPTIMIZER_YOSYSOPTIMIZER_H_
+#define INCLUDE_TRANSFORMS_YOSYSOPTIMIZER_YOSYSOPTIMIZER_H_
+
+#include "mlir/include/mlir/Pass/Pass.h"  // from @llvm-project
+
+namespace mlir {
+namespace heir {
+
+std::unique_ptr<Pass> createYosysOptimizer(std::string_view runfiles);
+
+#define GEN_PASS_DECL
+#include "include/Transforms/YosysOptimizer/YosysOptimizer.h.inc"
+
+#define GEN_PASS_REGISTRATION
+#include "include/Transforms/YosysOptimizer/YosysOptimizer.h.inc"
+
+}  // namespace heir
+}  // namespace mlir
+
+#endif  // INCLUDE_TRANSFORMS_YOSYSOPTIMIZER_YOSYSOPTIMIZER_H_

include/Transforms/YosysOptimizer/YosysOptimizer.td

@@ -0,0 +1,19 @@
+#ifndef INCLUDE_TRANSFORMS_YOSYSOPTIMIZER_YOSYSOPTIMIZER_TD_
+#define INCLUDE_TRANSFORMS_YOSYSOPTIMIZER_YOSYSOPTIMIZER_TD_
+
+include "mlir/Pass/PassBase.td"
+
+def YosysOptimizer : Pass<"yosys-optimizer"> {
+  let summary = "Invoke Yosys to perform circuit optimization.";
+
+  let description = [{
+    This pass invokes Yosys to convert an arithmetic circuit to an optimized
+    boolean circuit that uses the arith and comb dialects.
+  }];
+  let dependentDialects = [
+    "mlir::arith::ArithDialect",
+    "mlir::heir::comb::CombDialect",
+  ];
+}
+
+#endif  // INCLUDE_TRANSFORMS_YOSYSOPTIMIZER_YOSYSOPTIMIZER_TD_

lib/Transforms/YosysOptimizer/BUILD

@@ -0,0 +1,80 @@
+# YosysOptimizer pass
+
+package(
+    default_applicable_licenses = ["@heir//:license"],
+    default_visibility = ["//visibility:public"],
+)
+
+cc_library(
+    name = "RTLILImporter",
+    srcs = ["RTLILImporter.cpp"],
+    hdrs = ["RTLILImporter.h"],
+    deps = [
+        "@at_clifford_yosys//:kernel",
+        "@heir//lib/Dialect/Comb/IR:Dialect",
+        "@llvm-project//mlir:ArithDialect",
+        "@llvm-project//mlir:FuncDialect",
+        "@llvm-project//mlir:IR",
+        "@llvm-project//mlir:TransformUtils",
+    ],
+)
+
+cc_library(
+    name = "LUTImporter",
+    srcs = ["LUTImporter.cpp"],
+    hdrs = ["LUTImporter.h"],
+    deps = [
+        ":RTLILImporter",
+        "@at_clifford_yosys//:kernel",
+        "@heir//lib/Dialect/Comb/IR:Dialect",
+        "@llvm-project//llvm:Support",
+        "@llvm-project//mlir:ArithDialect",
+        "@llvm-project//mlir:FuncDialect",
+        "@llvm-project//mlir:IR",
+    ],
+)
+
+cc_test(
+    name = "LUTImporterTest",
+    size = "small",
+    srcs = ["LUTImporterTest.cpp"],
+    data = glob([
+        "tests/*.rtlil",
+    ]),
+    deps = [
+        ":LUTImporter",
+        "@at_clifford_yosys//:kernel",
+        "@at_clifford_yosys//:version",
+        "@googletest//:gtest",
+        "@heir//lib/Dialect/Comb/IR:Dialect",
+        "@llvm-project//mlir:ArithDialect",
+        "@llvm-project//mlir:IR",
+    ],
+)
+
+cc_library(
+    name = "YosysOptimizer",
+    srcs = ["YosysOptimizer.cpp"],
+    hdrs = [
+        "@heir//include/Transforms/YosysOptimizer:YosysOptimizer.h",
+    ],
+    data = [
+        ":yosys/map_lut_to_lut3.v",
+        "@at_clifford_yosys//:share_files",
+        "@edu_berkeley_abc//:abc",
+    ],
+    deps = [
+        ":LUTImporter",
+        "@at_clifford_yosys//:kernel",
+        "@at_clifford_yosys//:version",
+        "@bazel_tools//tools/cpp/runfiles",
+        "@heir//include/Transforms/YosysOptimizer:pass_inc_gen",
+        "@heir//lib/Dialect/Comb/IR:Dialect",
+        "@heir//lib/Target/Verilog:VerilogEmitter",
+        "@llvm-project//llvm:Support",
+        "@llvm-project//mlir:FuncDialect",
+        "@llvm-project//mlir:IR",
+        "@llvm-project//mlir:Pass",
+        "@llvm-project//mlir:Transforms",
+    ],
+)

lib/Transforms/YosysOptimizer/LUTImporter.cpp

@@ -0,0 +1,53 @@
+#include "lib/Transforms/YosysOptimizer/LUTImporter.h"
+
+#include "include/Dialect/Comb/IR/CombOps.h"
+#include "kernel/rtlil.h"  // from @at_clifford_yosys
+#include "llvm/include/llvm/Support/FormatVariadic.h"   // from @llvm-project
+#include "mlir/include/mlir/IR/ImplicitLocOpBuilder.h"  // from @llvm-project
+#include "mlir/include/mlir/IR/Operation.h"             // from @llvm-project
+
+namespace mlir {
+namespace heir {
+
+mlir::Operation *LUTImporter::createOp(Yosys::RTLIL::Cell *cell,
+                                       SmallVector<Value, 4> &inputs,
+                                       ImplicitLocOpBuilder &b) const {
+  assert(cell->type.begins_with("\\lut"));
+
+  // Create truth table from cell attributes.
+  int lutSize;
+  StringRef(cell->type.substr(4, 1)).getAsInteger(10, lutSize);
+  SmallVector<bool> lutValues(1 << lutSize, false);
+
+  for (int i = 0; i < lutValues.size(); i++) {
+    auto lutStr =
+        cell->getPort(Yosys::RTLIL::IdString(llvm::formatv("\\P{0}", i)));
+    lutValues[i] = lutStr.as_bool();
+  }
+
+  auto lookupTable = b.getBoolArrayAttr(llvm::ArrayRef<bool>(lutValues));
+  return b.create<comb::TruthTableOp>(inputs, lookupTable);
+}
+
+SmallVector<Yosys::RTLIL::SigSpec, 4> LUTImporter::getInputs(
+    Yosys::RTLIL::Cell *cell) const {
+  assert(cell->type.begins_with("\\lut") && "expected lut cells");
+
+  // Return all non-P, non-Y named attributes.
+  SmallVector<Yosys::RTLIL::SigSpec, 4> inputs;
+  for (auto &conn : cell->connections()) {
+    if (conn.first.contains("P") || conn.first.contains("Y")) {
+      continue;
+    }
+    inputs.push_back(conn.second);
+  }
+  return inputs;
+}
+
+Yosys::RTLIL::SigSpec LUTImporter::getOutput(Yosys::RTLIL::Cell *cell) const {
+  assert(cell->type.begins_with("\\lut"));
+  return cell->getPort(Yosys::RTLIL::IdString("\\Y"));
+}
+
+}  // namespace heir
+}  // namespace mlir

lib/Transforms/YosysOptimizer/LUTImporter.h

@@ -0,0 +1,28 @@
+#ifndef HEIR_LIB_TRANSFORMS_YOSYSOPTIMIZER_LUTIMPORTER_H_
+#define HEIR_LIB_TRANSFORMS_YOSYSOPTIMIZER_LUTIMPORTER_H_
+
+#include "kernel/rtlil.h"  // from @at_clifford_yosys
+#include "lib/Transforms/YosysOptimizer/RTLILImporter.h"
+
+namespace mlir {
+namespace heir {
+
+// LUTImporter implements the RTLILConfig for importing RTLIL that uses LUTs.
+class LUTImporter : public RTLILImporter {
+ public:
+  LUTImporter(MLIRContext *context) : RTLILImporter(context) {}
+
+ protected:
+  Operation *createOp(Yosys::RTLIL::Cell *cell, SmallVector<Value, 4> &inputs,
+                      ImplicitLocOpBuilder &b) const override;
+
+  SmallVector<Yosys::RTLIL::SigSpec, 4> getInputs(
+      Yosys::RTLIL::Cell *cell) const override;
+
+  Yosys::RTLIL::SigSpec getOutput(Yosys::RTLIL::Cell *cell) const override;
+};
+
+}  // namespace heir
+}  // namespace mlir
+
+#endif  // HEIR_LIB_TRANSFORMS_YOSYSOPTIMIZER_LUTIMPORTER_H_