Missing module

[ghost]

Wien, 5 July 19

Hi giulcioffi,

I was searching GitHub for some example SystemVerilog code and came across your upload, which looked so neat, I thought I'd try it out. Unfortunately, when I downloaded it and tried to run it in Questa, it seems to be missing the DUT itself:

** Error: /home/iala270035/WORK/SystemVerilog-Testbench-master/Gullfaxi/GullfaxiTOP.v(86): Module 'Gullfaxi' is not defined.

Is this something I am doing wrong or is it possible you could also upload the missing module as well please?

Kind regards,

Ian Lang