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add tests for 1-component vertex formats (and bgra)
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nolanderc committed Dec 2, 2024
1 parent 939e68f commit faac144
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Showing 4 changed files with 120 additions and 12 deletions.
71 changes: 69 additions & 2 deletions tests/tests/vertex_formats/draw.vert.wgsl
Original file line number Diff line number Diff line change
Expand Up @@ -223,8 +223,9 @@ struct AttributeBlock4{
@location(1) float32x2: vec2<f32>,
@location(2) float32x3: vec3<f32>,
@location(3) float32x4: vec4<f32>,
@location(4) float16x2: vec2<f32>,
@location(5) float16x4: vec4<f32>,
@location(4) float16: f32,
@location(5) float16x2: vec2<f32>,
@location(6) float16x4: vec4<f32>,
}

@vertex
Expand Down Expand Up @@ -252,6 +253,8 @@ fn vertex_block_4(v_in: AttributeBlock4) -> @builtin(position) vec4<f32>

// Accumulate all float16 into one checksum value.
var all_float16: f32 = 0.0;
all_float16 = accumulate_float16(all_float16, v_in.float16);

all_float16 = accumulate_float16(all_float16, v_in.float16x2.x);
all_float16 = accumulate_float16(all_float16, v_in.float16x2.y);

Expand Down Expand Up @@ -286,6 +289,70 @@ fn vertex_block_5(v_in: AttributeBlock5) -> @builtin(position) vec4<f32>
return vec4(0.0);
}

struct AttributeBlock6 {
@location(0) uint16: u32,
@location(1) sint16: i32,
@location(2) unorm16: f32,
@location(3) snorm16: f32,
@location(4) uint8: u32,
@location(5) sint8: i32,
@location(6) unorm8: f32,
@location(7) snorm8: f32,
}

@vertex
fn vertex_block_6(v_in: AttributeBlock6) -> @builtin(position) vec4<f32>
{
init_checksums();

// Accumulate all unorm into one checksum value.
var all_unorm: f32 = 0.0;
all_unorm = accumulate_unorm(all_unorm, v_in.unorm16);
all_unorm = accumulate_unorm(all_unorm, v_in.unorm8);
checksums[index_unorm] = f32(all_unorm);

// Accumulate all snorm into one checksum value.
var all_snorm: f32 = 0.0;
all_snorm = accumulate_snorm(all_snorm, v_in.snorm16);
all_snorm = accumulate_snorm(all_snorm, v_in.snorm8);
checksums[index_snorm] = f32(all_snorm);

// Accumulate all uint into one checksum value.
var all_uint: u32 = 0;
all_uint = accumulate_uint(all_uint, v_in.uint16);
all_uint = accumulate_uint(all_uint, v_in.uint8);
checksums[index_uint] = f32(all_uint);

// Accumulate all sint into one checksum value.
var all_sint: i32 = 0;
all_sint = accumulate_sint(all_sint, v_in.sint16);
all_sint = accumulate_sint(all_sint, v_in.sint8);
checksums[index_sint] = f32(all_sint);

return vec4(0.0);
}

struct AttributeBlock7 {
@location(0) unorm8x4_bgra: vec4<f32>,
}

@vertex
fn vertex_block_7(v_in: AttributeBlock7) -> @builtin(position) vec4<f32>
{
init_checksums();

// Accumulate all unorm into one checksum value.
var all_unorm: f32 = 0.0;
all_unorm = accumulate_unorm(all_unorm, v_in.unorm8x4_bgra.r);
all_unorm = accumulate_unorm(all_unorm, v_in.unorm8x4_bgra.g);
all_unorm = accumulate_unorm(all_unorm, v_in.unorm8x4_bgra.b);
all_unorm = accumulate_unorm(all_unorm, v_in.unorm8x4_bgra.a);

checksums[index_unorm] = f32(all_unorm);

return vec4(0.0);
}

fn accumulate_uint(accum: u32, val: u32) -> u32 {
return accum + val;
}
Expand Down
50 changes: 47 additions & 3 deletions tests/tests/vertex_formats/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,8 @@ enum TestCase {
SintsBig,
Floats,
Unorm1010102,
SingleSmallNormsAndInts,
Unorm8x4Bgra,
}

struct Test<'a> {
Expand Down Expand Up @@ -66,8 +68,24 @@ async fn vertex_formats_all(ctx: TestingContext) {
1 => Float32x2,
2 => Float32x3,
3 => Float32x4,
4 => Float16x2,
5 => Float16x4,
4 => Float16,
5 => Float16x2,
6 => Float16x4,
];

let attributes_block_6 = &wgpu::vertex_attr_array![
0 => Uint16,
1 => Sint16,
2 => Unorm16,
3 => Snorm16,
4 => Uint8,
5 => Sint8,
6 => Unorm8,
7 => Snorm8,
];

let attributes_block_7 = &wgpu::vertex_attr_array![
0 => Unorm8x4Bgra,
];

let tests = vec![
Expand Down Expand Up @@ -145,11 +163,37 @@ async fn vertex_formats_all(ctx: TestingContext) {
66u8, // Float32x3 (-2.0, -102.0, 100.0)
0u8, 0u8, 92u8, 66u8, 0u8, 0u8, 72u8, 194u8, 0u8, 0u8, 32u8, 65u8, 0u8, 0u8, 128u8,
63u8, // Float32x4 (55.0, -50.0, 10.0, 1.0)
0u8, 68u8, // Float16 (4.0)
0u8, 60u8, 72u8, 53u8, // Float16x2 (1.0, 0.33)
72u8, 57u8, 0u8, 192u8, 0u8, 188u8, 0u8,
184u8, // Float16x4 (0.66, -2.0, -1.0, -0.5)
],
checksums: &[0.0, 0.0, 0.0, 0.0, -1.5, 16.0],
checksums: &[0.0, 0.0, 0.0, 0.0, 2.5, 16.0],
},
Test {
case: TestCase::SingleSmallNormsAndInts,
entry_point: "vertex_block_6",
attributes: attributes_block_6,
input: &[
1u8, 2u8, // Uint16 (513)
1u8, 2u8, // Sint16 (513)
0u8, 64u8, // Unorm16 (0.25)
0u8, 64u8, // Snorm16 (0.5)
32u8, // Uint8 (32)
255u8, // Sint8 (-1)
128u8, // Unorm8 (0.5)
128u8, // Snorm8 (-1)
],
checksums: &[513.0 + 32.0, 513.0 - 1.0, 0.25 + 0.5, 0.5 - 1.0, 0.0, 0.0],
},
Test {
case: TestCase::Unorm8x4Bgra,
entry_point: "vertex_block_7",
attributes: attributes_block_7,
input: &[
128u8, 85u8, 170u8, 64u8, // Unorm8x4Bgra (0.67, 0.33, 0.5, 0.25)
],
checksums: &[0.0, 0.0, 1.75, 0.0, 0.0, 0.0],
},
];

Expand Down
2 changes: 1 addition & 1 deletion wgpu-hal/src/gles/conv.rs
Original file line number Diff line number Diff line change
Expand Up @@ -222,7 +222,7 @@ pub(super) fn describe_vertex_format(vertex_format: wgt::VertexFormat) -> super:
Vf::Sint32x4 => (4, glow::INT, Vak::Integer),
Vf::Float32x4 => (4, glow::FLOAT, Vak::Float),
Vf::Unorm10_10_10_2 => (4, glow::UNSIGNED_INT_10_10_10_2, Vak::Float),
Vf::Unorm8x4Bgra => (4, glow::BGRA, Vak::Float),
Vf::Unorm8x4Bgra => (glow::BGRA as i32, glow::UNSIGNED_BYTE, Vak::Float),
Vf::Float64 | Vf::Float64x2 | Vf::Float64x3 | Vf::Float64x4 => unimplemented!(),
};

Expand Down
9 changes: 3 additions & 6 deletions wgpu-types/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5286,7 +5286,8 @@ impl VertexFormat {
| Self::Float32
| Self::Uint32
| Self::Sint32
| Self::Unorm10_10_10_2 => 4,
| Self::Unorm10_10_10_2
| Self::Unorm8x4Bgra => 4,
Self::Uint16x4
| Self::Sint16x4
| Self::Unorm16x4
Expand All @@ -5297,11 +5298,7 @@ impl VertexFormat {
| Self::Sint32x2
| Self::Float64 => 8,
Self::Float32x3 | Self::Uint32x3 | Self::Sint32x3 => 12,
Self::Float32x4
| Self::Uint32x4
| Self::Sint32x4
| Self::Unorm8x4Bgra
| Self::Float64x2 => 16,
Self::Float32x4 | Self::Uint32x4 | Self::Sint32x4 | Self::Float64x2 => 16,
Self::Float64x3 => 24,
Self::Float64x4 => 32,
}
Expand Down

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