Regenerate on sdk-1.3.275.0

rspirv/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "rspirv"
-version = "0.12.0+sdk-1.3.268.0"
+version = "0.12.0+sdk-1.3.275.0"
 authors = ["Lei Zhang <[email protected]>"]
 edition = "2018"
 

rspirv/binary/autogen_parse_operand.rs

@@ -515,6 +515,12 @@ impl<'c, 'd> Parser<'c, 'd> {
  spirv::Decoration::ForcePow2DepthINTEL => {
  vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
  }
+ spirv::Decoration::StridesizeINTEL => {
+ vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+ }
+ spirv::Decoration::WordsizeINTEL => {
+ vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+ }
  spirv::Decoration::CacheSizeINTEL => {
  vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
  }
@@ -546,16 +552,6 @@ impl<'c, 'd> Parser<'c, 'd> {
  dr::Operand::LiteralBit32(self.decoder.bit32()?),
  dr::Operand::FPOperationMode(self.decoder.fp_operation_mode()?),
  ],
- spirv::Decoration::InitModeINTEL => vec![dr::Operand::InitializationModeQualifier(
- self.decoder.initialization_mode_qualifier()?,
- )],
- spirv::Decoration::ImplementInRegisterMapINTEL => {
- vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
- }
- spirv::Decoration::HostAccessINTEL => vec![
- dr::Operand::HostAccessQualifier(self.decoder.host_access_qualifier()?),
- dr::Operand::LiteralString(self.decoder.string()?),
- ],
  spirv::Decoration::FPMaxErrorDecorationINTEL => {
  vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
  }
@@ -587,6 +583,16 @@ impl<'c, 'd> Parser<'c, 'd> {
  spirv::Decoration::MMHostInterfaceWaitRequestINTEL => {
  vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
  }
+ spirv::Decoration::HostAccessINTEL => vec![
+ dr::Operand::HostAccessQualifier(self.decoder.host_access_qualifier()?),
+ dr::Operand::LiteralString(self.decoder.string()?),
+ ],
+ spirv::Decoration::InitModeINTEL => vec![dr::Operand::InitializationModeQualifier(
+ self.decoder.initialization_mode_qualifier()?,
+ )],
+ spirv::Decoration::ImplementInRegisterMapINTEL => {
+ vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+ }
  spirv::Decoration::CacheControlLoadINTEL => vec![
  dr::Operand::LiteralBit32(self.decoder.bit32()?),
  dr::Operand::LoadCacheControl(self.decoder.load_cache_control()?),

rspirv/dr/autogen_operand.rs

@@ -1369,6 +1369,9 @@ impl Operand {
  s::Decoration::StallEnableINTEL => {
  vec![spirv::Capability::FPGAClusterAttributesINTEL]
  }
+ s::Decoration::StallFreeINTEL => {
+ vec![spirv::Capability::FPGAClusterAttributesV2INTEL]
+ }
  s::Decoration::MathOpDSPModeINTEL => vec![spirv::Capability::FPGADSPControlINTEL],
  s::Decoration::InitiationIntervalINTEL
  | s::Decoration::MaxConcurrencyINTEL
@@ -1394,7 +1397,10 @@ impl Operand {
  | s::Decoration::SimpleDualPortINTEL
  | s::Decoration::MergeINTEL
  | s::Decoration::BankBitsINTEL
- | s::Decoration::ForcePow2DepthINTEL => {
+ | s::Decoration::ForcePow2DepthINTEL
+ | s::Decoration::StridesizeINTEL
+ | s::Decoration::WordsizeINTEL
+ | s::Decoration::TrueDualPortINTEL => {
  vec![spirv::Capability::FPGAMemoryAttributesINTEL]
  }
  s::Decoration::FPMaxErrorDecorationINTEL => {
@@ -1797,21 +1803,24 @@ impl Operand {
  | s::Capability::BitInstructions
  | s::Capability::AtomicFloat32AddEXT
  | s::Capability::AtomicFloat64AddEXT
- | s::Capability::LongConstantCompositeINTEL
+ | s::Capability::LongCompositesINTEL
  | s::Capability::OptNoneINTEL
  | s::Capability::AtomicFloat16AddEXT
  | s::Capability::DebugInfoModuleINTEL
  | s::Capability::BFloat16ConversionINTEL
  | s::Capability::SplitBarrierINTEL
- | s::Capability::GlobalVariableFPGADecorationsINTEL
- | s::Capability::GlobalVariableHostAccessINTEL
  | s::Capability::FPMaxErrorINTEL
  | s::Capability::FPGALatencyControlINTEL
  | s::Capability::FPGAArgumentInterfacesINTEL
+ | s::Capability::GlobalVariableHostAccessINTEL
+ | s::Capability::GlobalVariableFPGADecorationsINTEL
  | s::Capability::GroupUniformArithmeticKHR
  | s::Capability::CacheControlsINTEL => vec![],
  s::Capability::GenericPointer => vec![spirv::Capability::Addresses],
  s::Capability::SubgroupDispatch => vec![spirv::Capability::DeviceEnqueue],
+ s::Capability::FPGAClusterAttributesV2INTEL => {
+ vec![spirv::Capability::FPGAClusterAttributesINTEL]
+ }
  s::Capability::FPGAKernelAttributesv2INTEL => {
  vec![spirv::Capability::FPGAKernelAttributesINTEL]
  }
@@ -1913,7 +1922,6 @@ impl Operand {
  | s::Capability::FragmentShadingRateKHR
  | s::Capability::DrawParameters
  | s::Capability::WorkgroupMemoryExplicitLayoutKHR
- | s::Capability::WorkgroupMemoryExplicitLayout16BitAccessKHR
  | s::Capability::MultiView
  | s::Capability::VariablePointersStorageBuffer
  | s::Capability::RayQueryProvisionalKHR
@@ -1968,7 +1976,8 @@ impl Operand {
  vec![spirv::Capability::VariablePointersStorageBuffer]
  }
  s::Capability::VectorComputeINTEL => vec![spirv::Capability::VectorAnyINTEL],
- s::Capability::WorkgroupMemoryExplicitLayout8BitAccessKHR => {
+ s::Capability::WorkgroupMemoryExplicitLayout8BitAccessKHR
+ | s::Capability::WorkgroupMemoryExplicitLayout16BitAccessKHR => {
  vec![spirv::Capability::WorkgroupMemoryExplicitLayoutKHR]
  }
  },
@@ -2467,6 +2476,9 @@ impl Operand {
  | s::Decoration::UserSemantic
  | s::Decoration::FunctionRoundingModeINTEL
  | s::Decoration::FunctionDenormModeINTEL
+ | s::Decoration::StridesizeINTEL
+ | s::Decoration::WordsizeINTEL
+ | s::Decoration::TrueDualPortINTEL
  | s::Decoration::BurstCoalesceINTEL
  | s::Decoration::CacheSizeINTEL
  | s::Decoration::DontStaticallyCoalesceINTEL
@@ -2485,9 +2497,7 @@ impl Operand {
  | s::Decoration::SingleElementVectorINTEL
  | s::Decoration::VectorComputeCallableFunctionINTEL
  | s::Decoration::MediaBlockIOINTEL
- | s::Decoration::InitModeINTEL
- | s::Decoration::ImplementInRegisterMapINTEL
- | s::Decoration::HostAccessINTEL
+ | s::Decoration::StallFreeINTEL
  | s::Decoration::FPMaxErrorDecorationINTEL
  | s::Decoration::LatencyControlLabelINTEL
  | s::Decoration::LatencyControlConstraintINTEL
@@ -2500,6 +2510,9 @@ impl Operand {
  | s::Decoration::MMHostInterfaceMaxBurstINTEL
  | s::Decoration::MMHostInterfaceWaitRequestINTEL
  | s::Decoration::StableKernelArgumentINTEL
+ | s::Decoration::HostAccessINTEL
+ | s::Decoration::InitModeINTEL
+ | s::Decoration::ImplementInRegisterMapINTEL
  | s::Decoration::CacheControlLoadINTEL
  | s::Decoration::CacheControlStoreINTEL => vec![],
  s::Decoration::ExplicitInterpAMD => {
@@ -2855,7 +2868,8 @@ impl Operand {
  vec!["SPV_INTEL_fpga_argument_interfaces"]
  }
  s::Capability::FPGABufferLocationINTEL => vec!["SPV_INTEL_fpga_buffer_location"],
- s::Capability::FPGAClusterAttributesINTEL => {
+ s::Capability::FPGAClusterAttributesINTEL
+ | s::Capability::FPGAClusterAttributesV2INTEL => {
  vec!["SPV_INTEL_fpga_cluster_attributes"]
  }
  s::Capability::FPGADSPControlINTEL => vec!["SPV_INTEL_fpga_dsp_control"],
@@ -2883,9 +2897,7 @@ impl Operand {
  s::Capability::KernelAttributesINTEL
  | s::Capability::FPGAKernelAttributesINTEL
  | s::Capability::FPGAKernelAttributesv2INTEL => vec!["SPV_INTEL_kernel_attributes"],
- s::Capability::LongConstantCompositeINTEL => {
- vec!["SPV_INTEL_long_constant_composite"]
- }
+ s::Capability::LongCompositesINTEL => vec!["SPV_INTEL_long_composites"],
  s::Capability::LoopFuseINTEL => vec!["SPV_INTEL_loop_fuse"],
  s::Capability::SubgroupImageMediaBlockIOINTEL => vec!["SPV_INTEL_media_block_io"],
  s::Capability::MemoryAccessAliasingINTEL => {
@@ -3600,6 +3612,10 @@ impl Operand {
  kind: crate::grammar::OperandKind::LiteralInteger,
  quantifier: crate::grammar::OperandQuantifier::One,
  }],
+ s::Decoration::StridesizeINTEL => vec![crate::grammar::LogicalOperand {
+ kind: crate::grammar::OperandKind::LiteralInteger,
+ quantifier: crate::grammar::OperandQuantifier::One,
+ }],
  s::Decoration::FunctionDenormModeINTEL => vec![
  crate::grammar::LogicalOperand {
  kind: crate::grammar::OperandKind::LiteralInteger,
@@ -3636,6 +3652,10 @@ impl Operand {
  quantifier: crate::grammar::OperandQuantifier::One,
  }]
  }
+ s::Decoration::WordsizeINTEL => vec![crate::grammar::LogicalOperand {
+ kind: crate::grammar::OperandKind::LiteralInteger,
+ quantifier: crate::grammar::OperandQuantifier::One,
+ }],
  s::Decoration::XfbBuffer => vec![crate::grammar::LogicalOperand {
  kind: crate::grammar::OperandKind::LiteralInteger,
  quantifier: crate::grammar::OperandQuantifier::One,

rspirv/dr/build/autogen_norm_insts.rs

@@ -19436,6 +19436,47 @@ impl Builder {
  self.insert_into_block(insert_point, inst)?;
  Ok(_id)
  }
+ #[doc = "Appends an OpCompositeConstructContinuedINTEL instruction to the current block."]
+ pub fn composite_construct_continued_intel(
+ &mut self,
+ result_type: spirv::Word,
+ result_id: Option<spirv::Word>,
+ constituents: impl IntoIterator<Item = spirv::Word>,
+ ) -> BuildResult<spirv::Word> {
+ let _id = result_id.unwrap_or_else(|| self.id());
+ #[allow(unused_mut)]
+ let mut inst = dr::Instruction::new(
+ spirv::Op::CompositeConstructContinuedINTEL,
+ Some(result_type),
+ Some(_id),
+ vec![],
+ );
+ inst.operands
+ .extend(constituents.into_iter().map(dr::Operand::IdRef));
+ self.insert_into_block(InsertPoint::End, inst)?;
+ Ok(_id)
+ }
+ #[doc = "Appends an OpCompositeConstructContinuedINTEL instruction to the current block."]
+ pub fn insert_composite_construct_continued_intel(
+ &mut self,
+ insert_point: InsertPoint,
+ result_type: spirv::Word,
+ result_id: Option<spirv::Word>,
+ constituents: impl IntoIterator<Item = spirv::Word>,
+ ) -> BuildResult<spirv::Word> {
+ let _id = result_id.unwrap_or_else(|| self.id());
+ #[allow(unused_mut)]
+ let mut inst = dr::Instruction::new(
+ spirv::Op::CompositeConstructContinuedINTEL,
+ Some(result_type),
+ Some(_id),
+ vec![],
+ );
+ inst.operands
+ .extend(constituents.into_iter().map(dr::Operand::IdRef));
+ self.insert_into_block(insert_point, inst)?;
+ Ok(_id)
+ }
  #[doc = "Appends an OpConvertFToBF16INTEL instruction to the current block."]
  pub fn convert_f_to_bf16intel(
  &mut self,

rspirv/grammar/autogen_table.rs

@@ -6989,22 +6989,28 @@ static INSTRUCTION_TABLE: &[Instruction<'static>] = &[
  ),
  inst!(
  TypeStructContinuedINTEL,
- [LongConstantCompositeINTEL],
+ [LongCompositesINTEL],
  [],
  [(IdRef, ZeroOrMore)]
  ),
  inst!(
  ConstantCompositeContinuedINTEL,
- [LongConstantCompositeINTEL],
+ [LongCompositesINTEL],
  [],
  [(IdRef, ZeroOrMore)]
  ),
  inst!(
  SpecConstantCompositeContinuedINTEL,
- [LongConstantCompositeINTEL],
+ [LongCompositesINTEL],
  [],
  [(IdRef, ZeroOrMore)]
  ),
+ inst!(
+ CompositeConstructContinuedINTEL,
+ [LongCompositesINTEL],
+ [],
+ [(IdResultType, One), (IdResult, One), (IdRef, ZeroOrMore)]
+ ),
  inst!(
  ConvertFToBF16INTEL,
  [BFloat16ConversionINTEL],

rspirv/lift/autogen_context.rs

@@ -12058,6 +12058,19 @@ impl LiftContext {
  })
  .ok_or(OperandError::Missing)?,
  }),
+ 6096u32 => Ok(ops::Op::CompositeConstructContinuedINTEL {
+ constituents: {
+ let mut vec = Vec::new();
+ while let Some(item) = match operands.next() {
+ Some(dr::Operand::IdRef(value)) => Some(*value),
+ Some(_) => return Err(OperandError::WrongType.into()),
+ None => None,
+ } {
+ vec.push(item);
+ }
+ vec
+ },
+ }),
  6116u32 => Ok(ops::Op::ConvertFToBF16INTEL {
  float_value: (match operands.next() {
  Some(dr::Operand::IdRef(value)) => Some(*value),

rspirv/sr/autogen_decoration.rs

@@ -111,6 +111,9 @@ pub enum Decoration {
  MergeINTEL(String, String),
  BankBitsINTEL(Vec<u32>),
  ForcePow2DepthINTEL(u32),
+ StridesizeINTEL(u32),
+ WordsizeINTEL(u32),
+ TrueDualPortINTEL,
  BurstCoalesceINTEL,
  CacheSizeINTEL(u32),
  DontStaticallyCoalesceINTEL,
@@ -129,9 +132,7 @@ pub enum Decoration {
  SingleElementVectorINTEL,
  VectorComputeCallableFunctionINTEL,
  MediaBlockIOINTEL,
- InitModeINTEL(spirv::InitializationModeQualifier),
- ImplementInRegisterMapINTEL(u32),
- HostAccessINTEL(spirv::HostAccessQualifier, String),
+ StallFreeINTEL,
  FPMaxErrorDecorationINTEL(u32),
  LatencyControlLabelINTEL(u32),
  LatencyControlConstraintINTEL(u32, u32, u32),
@@ -144,6 +145,9 @@ pub enum Decoration {
  MMHostInterfaceMaxBurstINTEL(u32),
  MMHostInterfaceWaitRequestINTEL(u32),
  StableKernelArgumentINTEL,
+ HostAccessINTEL(spirv::HostAccessQualifier, String),
+ InitModeINTEL(spirv::InitializationModeQualifier),
+ ImplementInRegisterMapINTEL(u32),
  CacheControlLoadINTEL(u32, spirv::LoadCacheControl),
  CacheControlStoreINTEL(u32, spirv::StoreCacheControl),
 }

rspirv/sr/autogen_ops.rs

@@ -3013,6 +3013,9 @@ pub enum Op {
  semantics: spirv::Word,
  value: spirv::Word,
  },
+ CompositeConstructContinuedINTEL {
+ constituents: Vec<spirv::Word>,
+ },
  ConvertFToBF16INTEL {
  float_value: spirv::Word,
  },

spirv/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "spirv"
-version = "0.3.0+sdk-1.3.268.0"
+version = "0.3.0+sdk-1.3.275.0"
 authors = ["Lei Zhang <[email protected]>"]
 edition = "2018"
 
@@ -20,4 +20,4 @@ path = "lib.rs"
 
 [dependencies]
 bitflags = "2.0"
-serde = {version = "1", optional = true, features = ["derive"]}
+serde = { version = "1", optional = true, features = ["derive"] }