This project demonstrates the use of the Opsero Quad Gigabit Ethernet FMC and it supports several FPGA/MPSoC development boards. The design contains 4 AXI Ethernet blocks configured with DMAs.
Important links:
- The user guide for these reference designs is hosted here: AXI Ethernet for Ethernet FMC docs
- To report a bug: Report an issue.
- For technical support: Contact Opsero.
- To purchase the mezzanine card: Ethernet FMC order page.
This project is designed for version 2022.1 of the Xilinx tools (Vivado/Vitis/PetaLinux). If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.
In order to test this design on hardware, you will need the following:
- Vivado 2022.1
- Vitis 2022.1
- PetaLinux Tools 2022.1
- Ethernet FMC
- One of the supported evaluation boards
- Xilinx Soft TEMAC license
We strongly encourage community contribution to these projects. Please make a pull request if you would like to share your work:
- if you've spotted and fixed any issues
- if you've added designs for other target platforms
Thank you to everyone who supports us!
This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.
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