WIP: SoC: NSIM reorganization #7
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@evgeniy-paltsev, could you please take a look? |
dts/riscv/snps/rmx5xx.dtsi
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| @@ -0,0 +1,63 @@ | |||
| / { | |||
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As it doesn't represent any real SoC/board probably it worth to move it to board directory (as we have it for nSIM classic)
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tests/ztest/error_hook/src/main.c
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| @@ -60,7 +60,7 @@ __no_optimization static void trigger_fault_illegal_instruction(void) | |||
| */ | |||
| __no_optimization static void trigger_fault_access(void) | |||
| { | |||
| #if defined(CONFIG_SOC_ARC_IOT) || defined(CONFIG_SOC_NSIM) || defined(CONFIG_SOC_EMSK) | |||
| #if defined(CONFIG_SOC_ARC_IOT) || defined(SOC_FAMILY_NSIM_ARC_CLASSIC) || defined(CONFIG_SOC_EMSK) | |||
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Just for note: I'd expect that it's needed for all nSIM targets, not only for ARC_CLASSIC
| # nsim_isa_host_timer=0 | ||
| # nsim_isa_host_timer_mhz=50 |
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Let's drop this commented timer stuff
| cpu0_intc: interrupt-controller { | ||
| compatible = "riscv,cpu-intc"; | ||
| interrupt-controller; | ||
| #address-cells = <0>; | ||
| #interrupt-cells = <1>; | ||
| }; |
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I'm wondering what is this interrupt controller. I'd expect that CLINT should be the root interrupt controller.
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I'm not pretty sure about this part. It looks like interface for CLINT. And CLINT has reference to cpu0_intc
boards/snps/nsim/arc_v/rmx5xx.dtsi
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| device_type = "cpu"; | ||
| reg = <0>; | ||
| clock-frequency = <5000000>; | ||
| riscv,isa = "rv64imafdc"; |
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RV64 looks incorrect.
| #include "rmx500.dtsi" | ||
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| / { | ||
| model = "Synpsys Rmx500"; |
NSIM reorganization Signed-off-by: Nikolay Agishev <[email protected]>
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