Added Per-Page Instruction Description for RV32I

[AFOliveira]

Hello!

This PR introduces a continuation of the approach to instruction-per-page documentation for RISC-V that has been followed by newer extensions like "B", Vector crypto and Scalar crypto. We are actively trying to improve the process of documentation generation and believe that aligning the base ISA with these extensions would greatly increase the manual. We recognize that there might be things to improve and that we are fully open to address any feedback.

Key points:

• Enhanced instruction description structure:
  • Synopsis
  • Mnemonic
  • Encoding - with attributes
  • Description
  • Arguments
  • Operation (SAIL Code - retrieved from the SAIL repository)
  • Included in - (Extensions)
• Automated documentation generation:
  As discussed in Enhance RISC-V Instruction Documentation riscv/riscv-isa-manual#1590 we are also trying to achieve a nice automation process based on existing repos and minimizing our impact as we possible can. Please take note that, in order to achieve the most of this layout, we refined some of the SAIL Code by hand.

Current status:

• Proof of concept covering a subset of RISC-V instructions (RV32I)
• Example output available in the RISC-V instructions PDF riscv-unprivileged.pdf

There is a possibility here to impact the 200+ instructions in the manual that aren't still in this format if this approach is welcomed.

We welcome feedback on the approach, output quality, and potential modifications to existing repositories to support this effort.

Related issues: riscv#1470, riscv#1369, riscv#1253, riscv#1396, riscv#1567