MT Cannon: add cannon load/store opcodes tests #12196
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Signed-off-by: Chen Kai <[email protected]>
Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## develop #12196 +/- ##
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- Coverage 75.19% 74.97% -0.22%
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Files 49 49
Lines 3656 3656
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- Hits 2749 2741 -8
- Misses 734 743 +9
+ Partials 173 172 -1
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mbaxter
approved these changes
Oct 1, 2024
| imm = uint32(0x5) | ||
| } | ||
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| insn = tt.opcode<<26 | uint32(9)<<21 | uint32(8)<<16 | imm |
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(nit) For clarity, would be helpful to replace the magic numbers here with variables, something like:
Suggested change
| insn = tt.opcode<<26 | uint32(9)<<21 | uint32(8)<<16 | imm | |
| insn = tt.opcode<<26 | uint32(baseReg)<<21 | uint32(rtReg)<<16 | imm |
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| {name: "sb", opcode: uint32(0x28), rt: uint32(0xaa_bb_cc_dd), expectRes: uint32(0xaa_bb_cc_dd), expectMemVal: uint32(0xdd_00_00_00)}, // sb $t0, 4($t1) | ||
| {name: "sh", opcode: uint32(0x29), rt: uint32(0xaa_bb_cc_dd), expectRes: uint32(0xaa_bb_cc_dd), expectMemVal: uint32(0xcc_dd_00_00)}, // sh $t0, 4($t1) | ||
| {name: "swl", opcode: uint32(0x2a), rt: uint32(0xaa_bb_cc_dd), expectRes: uint32(0xaa_bb_cc_dd), expectMemVal: uint32(0xaa_bb_cc_dd)}, // swl $t0, 4($t1) | ||
| {name: "sw", opcode: uint32(0x2b), rt: uint32(0xaa_bb_cc_dd), expectRes: uint32(0xaa_bb_cc_dd), expectMemVal: uint32(0xaa_bb_cc_dd)}, // sw $t0, 4($t1) | ||
| {name: "swr unaligned address", opcode: uint32(0x2e), rt: uint32(0xaa_bb_cc_dd), isUnAligned: true, expectRes: uint32(0xaa_bb_cc_dd), expectMemVal: uint32(0xcc_dd_00_00)}, // swr $t0, 5($t1) | ||
| } |
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Store operations don't write back to a register, so I'd suggest cutting the expectedRes value for these, and only setting an expectation on the return register iff we have a value for expectedRes.
Signed-off-by: Chen Kai <[email protected]>
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Description
This PR add lb/lh/lw/lbu/lhu/lwl/lwr/sb/sh/swl/sw/swr tests
Tests
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