feat:add cannon add/addu/addi/addiu opcodes test

Signed-off-by: Chen Kai <[email protected]>

cannon/mipsevm/tests/evm_common_test.go

@@ -126,11 +126,7 @@ func TestEVMSingleStep_Jump(t *testing.T) {
  insn uint32
  expectNextPC uint32
  expectLink bool
- expectRS uint32
- expectRT uint32
- expectRD uint32
  }{
- {name: "add", pc: 0, nextPC: 4, insn: 0x02_32_40_20, expectNextPC: 8, expectRS: uint32(17), expectRT: uint32(18), expectRD: uint32(8)}, // add $t0, $s1, $s2
  {name: "j MSB set target", pc: 0, nextPC: 4, insn: 0x0A_00_00_02, expectNextPC: 0x08_00_00_08}, // j 0x02_00_00_02
  {name: "j non-zero PC region", pc: 0x10000000, nextPC: 0x10000004, insn: 0x08_00_00_02, expectNextPC: 0x10_00_00_08}, // j 0x2
  {name: "jal MSB set target", pc: 0, nextPC: 4, insn: 0x0E_00_00_02, expectNextPC: 0x08_00_00_08, expectLink: true}, // jal 0x02_00_00_02
@@ -154,15 +150,6 @@ func TestEVMSingleStep_Jump(t *testing.T) {
  if tt.expectLink {
  expected.Registers[31] = state.GetPC() + 8
  }
- if tt.expectRS != 0 {
- expected.Registers[tt.expectRD] = state.GetRegistersRef()[tt.expectRS]
- }
- if tt.expectRT != 0 {
- expected.Registers[tt.expectRD] = state.GetRegistersRef()[tt.expectRT]
- }
- if tt.expectRD != 0 {
- expected.Registers[tt.expectRD] = state.GetRegistersRef()[tt.expectRS] + state.GetRegistersRef()[tt.expectRT]
- }
 
  stepWitness, err := goVm.Step(true)
  require.NoError(t, err)
@@ -196,7 +183,7 @@ func TestEVMSingleStep_Add(t *testing.T) {
  {name: "addu", pc: 0, nextPC: 4, insn: 0x02_32_40_21, ifImm: false, rs: uint32(12), rt: uint32(20), expectNextPC: 8, expectRD: uint32(32)}, // addu t0, s1, s2
  {name: "addi", pc: 0, nextPC: 4, insn: 0x22_28_00_28, ifImm: true, rs: uint32(4), rt: uint32(1), imm: uint16(40), expectNextPC: 8, expectImm: uint32(44)}, // addi t0, s1, 40
  {name: "addi sign", pc: 0, nextPC: 4, insn: 0x22_28_ff_fe, ifImm: true, rs: uint32(2), rt: uint32(1), imm: uint16(0xfffe), expectNextPC: 8, expectImm: uint32(0)}, // addi t0, s1, -2
- {name: "addui", pc: 0, nextPC: 4, insn: 0x26_28_00_28, ifImm: true, rs: uint32(4), rt: uint32(1), imm: uint16(40), expectNextPC: 8, expectImm: uint32(44)}, // addiu t0, s1, 40
+ {name: "addiu", pc: 0, nextPC: 4, insn: 0x26_28_00_28, ifImm: true, rs: uint32(4), rt: uint32(1), imm: uint16(40), expectNextPC: 8, expectImm: uint32(44)}, // addiu t0, s1, 40
  }
 
  for _, v := range versions {