feat(esp-coredump): add esp32c61 chip support

espressif · Sep 4, 2024 · 7b75c8a · 7b75c8a
1 parent 8476558
commit 7b75c8a
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Showing 6 changed files with 24 additions and 5 deletions.
diff --git a/esp_coredump/coredump.py b/esp_coredump/coredump.py
@@ -207,6 +207,9 @@ def get_target(self): # type: () -> str
  if chip_version == EspCoreDumpVersion.ESP32C5:
  return 'esp32c5'
 
+ if chip_version == EspCoreDumpVersion.ESP32C61:
+ return 'esp32c61'
+
  target = None
  try:
  inst = detect_chip(self.port, self.baud)

diff --git a/esp_coredump/corefile/__init__.py b/esp_coredump/corefile/__init__.py
@@ -16,7 +16,7 @@
 ]
 
 XTENSA_TARGETS = ['esp32', 'esp32s2', 'esp32s3']
-RISCV_TARGETS = ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5']
+RISCV_TARGETS = ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61']
 SUPPORTED_TARGETS = XTENSA_TARGETS + RISCV_TARGETS
 
 

diff --git a/esp_coredump/corefile/loader.py b/esp_coredump/corefile/loader.py
@@ -22,7 +22,8 @@
 from .elf import (TASK_STATUS_CORRECT, TASK_STATUS_TCB_CORRUPTED, ElfFile,
  ElfSegment, ESPCoreDumpElfFile, EspTaskStatus, NoteSection)
 from .riscv import (Esp32C2Methods, Esp32C3Methods, Esp32C5Methods,
- Esp32C6Methods, Esp32H2Methods, Esp32P4Methods)
+ Esp32C6Methods, Esp32C61Methods, Esp32H2Methods,
+ Esp32P4Methods)
 from .xtensa import Esp32Methods, Esp32S2Methods, Esp32S3Methods
 
 IDF_PATH = os.getenv('IDF_PATH', '')
@@ -114,8 +115,9 @@ class EspCoreDumpVersion(object):
  ESP32C6 = 13
  ESP32H2 = 16
  ESP32P4 = 18
+ ESP32C61 = 20
  ESP32C5 = 23
- RISCV_CHIPS = [ESP32C3, ESP32C2, ESP32H2, ESP32C6, ESP32P4, ESP32C5]
+ RISCV_CHIPS = [ESP32C3, ESP32C2, ESP32H2, ESP32C6, ESP32P4, ESP32C5, ESP32C61]
 
  COREDUMP_SUPPORTED_TARGETS = XTENSA_CHIPS + RISCV_CHIPS
 
@@ -255,6 +257,8 @@ def _load_core_src(self): # type: () -> str
  self.target_methods = Esp32P4Methods() # type: ignore
  elif self.chip_ver == self.ESP32C5:
  self.target_methods = Esp32C5Methods() # type: ignore
+ elif self.chip_ver == self.ESP32C61:
+ self.target_methods = Esp32C61Methods() # type: ignore
  else:
  raise NotImplementedError
  else:

diff --git a/esp_coredump/corefile/riscv.py b/esp_coredump/corefile/riscv.py
@@ -68,3 +68,7 @@ class Esp32P4Methods(BaseTargetMethods, RiscvMethodsMixin):
 
 class Esp32C5Methods(BaseTargetMethods, RiscvMethodsMixin):
  TARGET = 'esp32c5'
+
+
+class Esp32C61Methods(BaseTargetMethods, RiscvMethodsMixin):
+ TARGET = 'esp32c61'
diff --git a/esp_coredump/corefile/soc_headers/esp32c61.py b/esp_coredump/corefile/soc_headers/esp32c61.py
@@ -0,0 +1,8 @@
+SOC_IRAM_LOW = 0x40800000
+SOC_IRAM_HIGH = 0x40850000
+SOC_DRAM_LOW = 0x40800000
+SOC_DRAM_HIGH = 0x40850000
+SOC_RTC_DRAM_LOW = 0xffffffff
+SOC_RTC_DRAM_HIGH = 0xffffffff
+SOC_RTC_DATA_LOW = 0xffffffff
+SOC_RTC_DATA_HIGH = 0xffffffff
diff --git a/tests/README.md b/tests/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | ESP32-P4 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C61 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
 
 # ESP Core Dump Tests