Remove core-isa-parser package, prepare to transfer packages (#41)

* Derive `serde` traits for `core-isa-parser` types, serialize parsed ISA config to TOML files

* Remove the `core-isa-parser` package entirely

* Fix some warnings in `xtensa-lx-rt`

* Add notice to `README.md` stating that the packages have moved

README.md

@@ -1,18 +1,22 @@
 # xtensa-lx crates
 
+---
+
+## This project has moved! It can now be found in the [esp-rs/esp-hal](https://github.com/esp-rs/esp-hal/) repository.
+
+---
+
 This repository contains various crates useful for writing Rust programs
 on xtensa-lx microcontrollers:
 
-* [`xtensa-lx`]: CPU peripheral access and intrinsics.
-* [`xtensa-lx-rt`]: Startup code and interrupt handling.
-* [`core-isa-parser`]: A parser for XCHAL ISA configuration files.
+- [`xtensa-lx`]: CPU peripheral access and intrinsics.
+- [`xtensa-lx-rt`]: Startup code and interrupt handling.
 
 [`xtensa-lx`]: https://crates.io/crates/xtensa-lx
 [`xtensa-lx-rt`]: https://crates.io/crates/xtensa-lx-rt
-[`core-isa-parser`]: https://crates.io/crates/core-isa-parser
 
 ### Contribution
 
 Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the
 work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any
-additional terms or conditions.
+additional terms or conditions.

xtensa-lx-rt/Cargo.toml

@@ -20,8 +20,12 @@ r0                = "1.0.0"
 xtensa-lx         = { version = "0.9.0", path = "../xtensa-lx" }
 
 [build-dependencies]
-core-isa-parser = { version = "0.2.0", path = "../core-isa-parser" }
-minijinja       = "1.0.16"
+anyhow          = "1.0.86"
+enum-as-inner   = "0.6.0"
+minijinja       = "2.0.3"
+serde           = { version = "1.0.204", features = ["derive"] }
+strum           = { version = "0.26.3", features = ["derive"] }
+toml            = "0.8.10"
 
 [features]
 ## Save and restore float registers for exceptions

xtensa-lx-rt/build.rs

@@ -1,33 +1,76 @@
 use std::{
     collections::{HashMap, HashSet},
     env,
-    fs::File,
+    fs::{self, File},
     io::Write,
     path::PathBuf,
 };
 
-use core_isa_parser::{get_config, Chip, Value};
+use anyhow::Result;
+use enum_as_inner::EnumAsInner;
 use minijinja::{context, Environment};
+use serde::Deserialize;
+use strum::{Display, EnumIter, EnumString};
+
+/// The chips which are present in the xtensa-overlays repository
+///
+/// When `.to_string()` is called on a variant, the resulting string is the path
+/// to the chip's corresponding directory.
+#[derive(Debug, Clone, Copy, PartialEq, Display, EnumIter, Deserialize)]
+enum Chip {
+    #[strum(to_string = "xtensa_esp32")]
+    Esp32,
+    #[strum(to_string = "xtensa_esp32s2")]
+    Esp32s2,
+    #[strum(to_string = "xtensa_esp32s3")]
+    Esp32s3,
+}
+
+/// The valid interrupt types declared in the `core-isa.h` headers
+#[derive(Debug, Clone, Copy, PartialEq, EnumString, Deserialize)]
+enum InterruptType {
+    #[strum(serialize = "XTHAL_INTTYPE_EXTERN_EDGE")]
+    ExternEdge,
+    #[strum(serialize = "XTHAL_INTTYPE_EXTERN_LEVEL")]
+    ExternLevel,
+    #[strum(serialize = "XTHAL_INTTYPE_NMI")]
+    Nmi,
+    #[strum(serialize = "XTHAL_INTTYPE_PROFILING")]
+    Profiling,
+    #[strum(serialize = "XTHAL_INTTYPE_SOFTWARE")]
+    Software,
+    #[strum(serialize = "XTHAL_INTTYPE_TIMER")]
+    Timer,
+    #[strum(serialize = "XTHAL_TIMER_UNCONFIGURED")]
+    TimerUnconfigured,
+}
+
+/// The allowable value types for definitions
+#[derive(Debug, Clone, PartialEq, EnumAsInner, Deserialize)]
+enum Value {
+    Integer(i64),
+    Interrupt(InterruptType),
+    String(String),
+}
 
-fn main() {
+fn main() -> Result<()> {
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
 
     // Put the linker script somewhere the linker can find it
-    File::create(out.join("link.x"))
-        .unwrap()
-        .write_all(include_bytes!("xtensa.in.x"))
-        .unwrap();
-
     println!("cargo:rustc-link-search={}", out.display());
 
-    handle_esp32();
+    File::create(out.join("link.x"))?.write_all(include_bytes!("xtensa.in.x"))?;
+
+    handle_esp32()?;
 
     // Only re-run the build script when xtensa.in.x is changed,
     // instead of when any part of the source code changes.
     println!("cargo:rerun-if-changed=xtensa.in.x");
+
+    Ok(())
 }
 
-fn handle_esp32() {
+fn handle_esp32() -> Result<()> {
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
 
     let rustflags = env::var_os("CARGO_ENCODED_RUSTFLAGS")
@@ -67,43 +110,50 @@ fn handle_esp32() {
         (false, false, true) => Chip::Esp32s3,
         _ => panic!("Either the esp32, esp32s2, esp32s3 feature must be enabled"),
     };
-    let isa_config = get_config(chip).expect("Unable to parse ISA config");
+
+    let isa_toml = fs::read_to_string(format!("config/{chip}.toml"))?;
+    let isa_config: HashMap<String, Value> = toml::from_str(&isa_toml)?;
 
     inject_cfgs(&isa_config, &features_to_disable);
     inject_cpu_cfgs(&isa_config);
-    generate_exception_x(&out, &isa_config);
-    generate_interrupt_level_masks(&out, &isa_config);
+    generate_exception_x(&out, &isa_config)?;
+    generate_interrupt_level_masks(&out, &isa_config)?;
+
+    Ok(())
 }
 
-fn generate_interrupt_level_masks(out: &PathBuf, isa_config: &HashMap<String, Value>) {
-    let mut env = Environment::new();
+fn generate_interrupt_level_masks(
+    out: &PathBuf,
+    isa_config: &HashMap<String, Value>,
+) -> Result<()> {
     let exception_source_template = &include_str!("interrupt_level_masks.rs.jinja")[..];
-    env.add_template("interrupt_level_masks.rs", exception_source_template)
-        .unwrap();
+
+    let mut env = Environment::new();
+    env.add_template("interrupt_level_masks.rs", exception_source_template)?;
+
     let template = env.get_template("interrupt_level_masks.rs").unwrap();
-    let exception_source = template
-        .render(context! {
-            XCHAL_INTLEVEL1_MASK => isa_config.get("XCHAL_INTLEVEL1_MASK").unwrap().as_integer(),
-            XCHAL_INTLEVEL2_MASK => isa_config.get("XCHAL_INTLEVEL2_MASK").unwrap().as_integer(),
-            XCHAL_INTLEVEL3_MASK => isa_config.get("XCHAL_INTLEVEL3_MASK").unwrap().as_integer(),
-            XCHAL_INTLEVEL4_MASK => isa_config.get("XCHAL_INTLEVEL4_MASK").unwrap().as_integer(),
-            XCHAL_INTLEVEL5_MASK => isa_config.get("XCHAL_INTLEVEL5_MASK").unwrap().as_integer(),
-            XCHAL_INTLEVEL6_MASK => isa_config.get("XCHAL_INTLEVEL6_MASK").unwrap().as_integer(),
-            XCHAL_INTLEVEL7_MASK => isa_config.get("XCHAL_INTLEVEL7_MASK").unwrap().as_integer(),
-        })
-        .unwrap();
-    File::create(out.join("interrupt_level_masks.rs"))
-        .unwrap()
-        .write_all(exception_source.as_bytes())
-        .unwrap();
+    let exception_source = template.render(context! {
+        XCHAL_INTLEVEL1_MASK => isa_config.get("XCHAL_INTLEVEL1_MASK").unwrap().as_integer(),
+        XCHAL_INTLEVEL2_MASK => isa_config.get("XCHAL_INTLEVEL2_MASK").unwrap().as_integer(),
+        XCHAL_INTLEVEL3_MASK => isa_config.get("XCHAL_INTLEVEL3_MASK").unwrap().as_integer(),
+        XCHAL_INTLEVEL4_MASK => isa_config.get("XCHAL_INTLEVEL4_MASK").unwrap().as_integer(),
+        XCHAL_INTLEVEL5_MASK => isa_config.get("XCHAL_INTLEVEL5_MASK").unwrap().as_integer(),
+        XCHAL_INTLEVEL6_MASK => isa_config.get("XCHAL_INTLEVEL6_MASK").unwrap().as_integer(),
+        XCHAL_INTLEVEL7_MASK => isa_config.get("XCHAL_INTLEVEL7_MASK").unwrap().as_integer(),
+    })?;
+
+    File::create(out.join("interrupt_level_masks.rs"))?.write_all(exception_source.as_bytes())?;
+
+    Ok(())
 }
 
-fn generate_exception_x(out: &PathBuf, isa_config: &HashMap<String, Value>) {
-    let mut env = Environment::new();
+fn generate_exception_x(out: &PathBuf, isa_config: &HashMap<String, Value>) -> Result<()> {
     let exception_source_template = &include_str!("exception-esp32.x.jinja")[..];
-    env.add_template("exception.x", exception_source_template)
-        .unwrap();
-    let template = env.get_template("exception.x").unwrap();
+
+    let mut env = Environment::new();
+    env.add_template("exception.x", exception_source_template)?;
+
+    let template = env.get_template("exception.x")?;
     let exception_source = template.render(
         context! {
             XCHAL_WINDOW_OF4_VECOFS => isa_config.get("XCHAL_WINDOW_OF4_VECOFS").unwrap().as_integer(),
@@ -122,11 +172,11 @@ fn generate_exception_x(out: &PathBuf, isa_config: &HashMap<String, Value>) {
             XCHAL_USER_VECOFS => isa_config.get("XCHAL_USER_VECOFS").unwrap().as_integer(),
             XCHAL_DOUBLEEXC_VECOFS => isa_config.get("XCHAL_DOUBLEEXC_VECOFS").unwrap().as_integer(),
         }
-    ).unwrap();
-    File::create(out.join("exception.x"))
-        .unwrap()
-        .write_all(exception_source.as_bytes())
-        .unwrap();
+    )?;
+
+    File::create(out.join("exception.x"))?.write_all(exception_source.as_bytes())?;
+
+    Ok(())
 }
 
 fn inject_cfgs(isa_config: &HashMap<String, Value>, disabled_features: &HashSet<String>) {