Define reserved bits in RMT_SYS_CONF_REG for C6/H2

esp-rs · Oct 22, 2024 · 262388a · 262388a
1 parent 317f89c
commit 262388a
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diff --git a/esp32c6/src/rmt/sys_conf.rs b/esp32c6/src/rmt/sys_conf.rs
@@ -18,26 +18,6 @@ pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type MEM_FORCE_PU_R = crate::BitReader;
 #[doc = "Field `MEM_FORCE_PU` writer - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
 pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor"]
-pub type SCLK_DIV_NUM_R = crate::FieldReader;
-#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor"]
-pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
-#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_A_R = crate::FieldReader;
-#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
-#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_B_R = crate::FieldReader;
-#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
-#[doc = "Field `SCLK_SEL` reader - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-pub type SCLK_SEL_R = crate::FieldReader;
-#[doc = "Field `SCLK_SEL` writer - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `SCLK_ACTIVE` reader - rmt_sclk switch"]
-pub type SCLK_ACTIVE_R = crate::BitReader;
-#[doc = "Field `SCLK_ACTIVE` writer - rmt_sclk switch"]
-pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CLK_EN` reader - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
 pub type CLK_EN_R = crate::BitReader;
 #[doc = "Field `CLK_EN` writer - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
@@ -63,31 +43,6 @@ impl R {
     pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R {
         MEM_FORCE_PU_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bits 4:11 - the integral part of the fractional divisor"]
-    #[inline(always)]
-    pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R {
-        SCLK_DIV_NUM_R::new(((self.bits >> 4) & 0xff) as u8)
-    }
-    #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    pub fn sclk_div_a(&self) -> SCLK_DIV_A_R {
-        SCLK_DIV_A_R::new(((self.bits >> 12) & 0x3f) as u8)
-    }
-    #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    pub fn sclk_div_b(&self) -> SCLK_DIV_B_R {
-        SCLK_DIV_B_R::new(((self.bits >> 18) & 0x3f) as u8)
-    }
-    #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-    #[inline(always)]
-    pub fn sclk_sel(&self) -> SCLK_SEL_R {
-        SCLK_SEL_R::new(((self.bits >> 24) & 3) as u8)
-    }
-    #[doc = "Bit 26 - rmt_sclk switch"]
-    #[inline(always)]
-    pub fn sclk_active(&self) -> SCLK_ACTIVE_R {
-        SCLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0)
-    }
     #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
     #[inline(always)]
     pub fn clk_en(&self) -> CLK_EN_R {
@@ -102,11 +57,6 @@ impl core::fmt::Debug for R {
             .field("mem_clk_force_on", &self.mem_clk_force_on())
             .field("mem_force_pd", &self.mem_force_pd())
             .field("mem_force_pu", &self.mem_force_pu())
-            .field("sclk_div_num", &self.sclk_div_num())
-            .field("sclk_div_a", &self.sclk_div_a())
-            .field("sclk_div_b", &self.sclk_div_b())
-            .field("sclk_sel", &self.sclk_sel())
-            .field("sclk_active", &self.sclk_active())
             .field("clk_en", &self.clk_en())
             .finish()
     }
@@ -136,36 +86,6 @@ impl W {
     pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<SYS_CONF_SPEC> {
         MEM_FORCE_PU_W::new(self, 3)
     }
-    #[doc = "Bits 4:11 - the integral part of the fractional divisor"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<SYS_CONF_SPEC> {
-        SCLK_DIV_NUM_W::new(self, 4)
-    }
-    #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<SYS_CONF_SPEC> {
-        SCLK_DIV_A_W::new(self, 12)
-    }
-    #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<SYS_CONF_SPEC> {
-        SCLK_DIV_B_W::new(self, 18)
-    }
-    #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_sel(&mut self) -> SCLK_SEL_W<SYS_CONF_SPEC> {
-        SCLK_SEL_W::new(self, 24)
-    }
-    #[doc = "Bit 26 - rmt_sclk switch"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<SYS_CONF_SPEC> {
-        SCLK_ACTIVE_W::new(self, 26)
-    }
     #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
     #[inline(always)]
     #[must_use]

diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml
@@ -468,4 +468,12 @@ DMA:
 
 ASSIST_DEBUG:
   _include: ../../../common_patches/assist_debug.yaml
-
+
+RMT:
+  SYS_CONF:
+    _delete:
+      - SCLK_DIV_NUM
+      - SCLK_DIV_A
+      - SCLK_DIV_B
+      - SCLK_SEL
+      - SCLK_ACTIVE
diff --git a/esp32h2/src/rmt/sys_conf.rs b/esp32h2/src/rmt/sys_conf.rs
@@ -18,26 +18,6 @@ pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type MEM_FORCE_PU_R = crate::BitReader;
 #[doc = "Field `MEM_FORCE_PU` writer - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
 pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor"]
-pub type SCLK_DIV_NUM_R = crate::FieldReader;
-#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor"]
-pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
-#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_A_R = crate::FieldReader;
-#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
-#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_B_R = crate::FieldReader;
-#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor"]
-pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
-#[doc = "Field `SCLK_SEL` reader - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-pub type SCLK_SEL_R = crate::FieldReader;
-#[doc = "Field `SCLK_SEL` writer - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `SCLK_ACTIVE` reader - rmt_sclk switch"]
-pub type SCLK_ACTIVE_R = crate::BitReader;
-#[doc = "Field `SCLK_ACTIVE` writer - rmt_sclk switch"]
-pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CLK_EN` reader - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
 pub type CLK_EN_R = crate::BitReader;
 #[doc = "Field `CLK_EN` writer - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
@@ -63,31 +43,6 @@ impl R {
     pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R {
         MEM_FORCE_PU_R::new(((self.bits >> 3) & 1) != 0)
     }
-    #[doc = "Bits 4:11 - the integral part of the fractional divisor"]
-    #[inline(always)]
-    pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R {
-        SCLK_DIV_NUM_R::new(((self.bits >> 4) & 0xff) as u8)
-    }
-    #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    pub fn sclk_div_a(&self) -> SCLK_DIV_A_R {
-        SCLK_DIV_A_R::new(((self.bits >> 12) & 0x3f) as u8)
-    }
-    #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    pub fn sclk_div_b(&self) -> SCLK_DIV_B_R {
-        SCLK_DIV_B_R::new(((self.bits >> 18) & 0x3f) as u8)
-    }
-    #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-    #[inline(always)]
-    pub fn sclk_sel(&self) -> SCLK_SEL_R {
-        SCLK_SEL_R::new(((self.bits >> 24) & 3) as u8)
-    }
-    #[doc = "Bit 26 - rmt_sclk switch"]
-    #[inline(always)]
-    pub fn sclk_active(&self) -> SCLK_ACTIVE_R {
-        SCLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0)
-    }
     #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
     #[inline(always)]
     pub fn clk_en(&self) -> CLK_EN_R {
@@ -102,11 +57,6 @@ impl core::fmt::Debug for R {
             .field("mem_clk_force_on", &self.mem_clk_force_on())
             .field("mem_force_pd", &self.mem_force_pd())
             .field("mem_force_pu", &self.mem_force_pu())
-            .field("sclk_div_num", &self.sclk_div_num())
-            .field("sclk_div_a", &self.sclk_div_a())
-            .field("sclk_div_b", &self.sclk_div_b())
-            .field("sclk_sel", &self.sclk_sel())
-            .field("sclk_active", &self.sclk_active())
             .field("clk_en", &self.clk_en())
             .finish()
     }
@@ -136,36 +86,6 @@ impl W {
     pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<SYS_CONF_SPEC> {
         MEM_FORCE_PU_W::new(self, 3)
     }
-    #[doc = "Bits 4:11 - the integral part of the fractional divisor"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<SYS_CONF_SPEC> {
-        SCLK_DIV_NUM_W::new(self, 4)
-    }
-    #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<SYS_CONF_SPEC> {
-        SCLK_DIV_A_W::new(self, 12)
-    }
-    #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<SYS_CONF_SPEC> {
-        SCLK_DIV_B_W::new(self, 18)
-    }
-    #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_sel(&mut self) -> SCLK_SEL_W<SYS_CONF_SPEC> {
-        SCLK_SEL_W::new(self, 24)
-    }
-    #[doc = "Bit 26 - rmt_sclk switch"]
-    #[inline(always)]
-    #[must_use]
-    pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<SYS_CONF_SPEC> {
-        SCLK_ACTIVE_W::new(self, 26)
-    }
     #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
     #[inline(always)]
     #[must_use]

diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml
@@ -484,3 +484,12 @@ TWAI0:
 
 ASSIST_DEBUG:
   _include: ../../../common_patches/assist_debug.yaml
+
+RMT:
+  SYS_CONF:
+    _delete:
+      - SCLK_DIV_NUM
+      - SCLK_DIV_A
+      - SCLK_DIV_B
+      - SCLK_SEL
+      - SCLK_ACTIVE