Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Remove unnecessary features from esp-hal-procmacros, enable rtc-slow feature for Xtensa devices #2594

Merged
merged 4 commits into from
Nov 25, 2024
Merged
Show file tree
Hide file tree
Changes from 3 commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions esp-hal-procmacros/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

### Removed

- Removed the `enum-dispatch`, `interrupt`, and `ram` features (#2594)

## [0.15.0] - 2024-11-20

### Changed
Expand Down
14 changes: 4 additions & 10 deletions esp-hal-procmacros/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -17,24 +17,18 @@ proc-macro = true
darling = "0.20.10"
document-features = "0.2.10"
litrs = "0.4.1"
object = { version = "0.36.5", optional = true, default-features = false, features = ["read_core", "elf"] }
object = { version = "0.36.5", default-features = false, features = ["read_core", "elf"], optional = true }
proc-macro-crate = "3.2.0"
proc-macro-error2 = "2.0.1"
proc-macro2 = "1.0.89"
proc-macro2 = "1.0.92"
quote = "1.0.37"
syn = { version = "2.0.87", features = ["extra-traits", "full"] }
syn = { version = "2.0.89", features = ["extra-traits", "full"] }

[features]
## Provide a `#[main]` procmacro to mark the entry point for Embassy applications.
embassy = []
## Provide enum dispatch helpers.
enum-dispatch = []
## Provide an `#[interrupt]` procmacro for defining interrupt service routines.
interrupt = []
## Provide a `#[ram]` procmacro to place functions in RAM instead of flash.
ram = []
## Indicates the target device has RTC slow memory available.
rtc_slow = []
rtc-slow = []

#! ### Low-power Core Feature Flags
## Indicate that the SoC contains an LP core.
Expand Down
33 changes: 11 additions & 22 deletions esp-hal-procmacros/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -47,12 +47,17 @@
#![doc = document_features::document_features!()]
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]

#[allow(unused)]
use proc_macro::TokenStream;
use darling::{ast::NestedMeta, Error, FromMeta};
use proc_macro::{Span, TokenStream};
use proc_macro2::Ident;
use proc_macro_crate::{crate_name, FoundCrate};
use proc_macro_error2::abort;
use syn::{parse, parse::Error as ParseError, spanned::Spanned, Item, ItemFn, ReturnType, Type};

use self::interrupt::{check_attr_whitelist, WhiteListCaller};

#[cfg(feature = "embassy")]
mod embassy;
#[cfg(feature = "interrupt")]
mod interrupt;
#[cfg(any(
feature = "is-lp-core",
Expand All @@ -62,7 +67,6 @@ mod interrupt;
))]
mod lp_core;

#[cfg(feature = "ram")]
#[derive(Debug, Default, darling::FromMeta)]
#[darling(default)]
struct RamArgs {
Expand All @@ -80,7 +84,7 @@ struct RamArgs {
/// # Options
///
/// - `rtc_fast`: Use RTC fast RAM.
/// - `rtc_slow`: Use RTC slow RAM. **Note**: not available on all targets
/// - `rtc_slow`: Use RTC slow RAM. **Note**: not available on all targets.
/// - `persistent`: Persist the contents of the `static` across resets. See [the
/// section below](#persistent) for details.
/// - `zeroed`: Initialize the memory of the `static` to zero. The initializer
Expand Down Expand Up @@ -126,15 +130,9 @@ struct RamArgs {
///
/// [`bytemuck::AnyBitPattern`]: https://docs.rs/bytemuck/1.9.0/bytemuck/trait.AnyBitPattern.html
/// [`bytemuck::Zeroable`]: https://docs.rs/bytemuck/1.9.0/bytemuck/trait.Zeroable.html
#[cfg(feature = "ram")]
#[proc_macro_attribute]
#[proc_macro_error2::proc_macro_error]
pub fn ram(args: TokenStream, input: TokenStream) -> TokenStream {
use darling::{ast::NestedMeta, Error, FromMeta};
use proc_macro::Span;
use proc_macro_error2::abort;
use syn::{parse, Item};

let attr_args = match NestedMeta::parse_meta_list(args.into()) {
Ok(v) => v,
Err(e) => {
Expand All @@ -156,7 +154,7 @@ pub fn ram(args: TokenStream, input: TokenStream) -> TokenStream {

let item: Item = parse(input).expect("failed to parse input");

#[cfg(not(feature = "rtc_slow"))]
#[cfg(not(feature = "rtc-slow"))]
if rtc_slow {
abort!(
Span::call_site(),
Expand Down Expand Up @@ -206,7 +204,7 @@ pub fn ram(args: TokenStream, input: TokenStream) -> TokenStream {
let trait_check = trait_check.map(|name| {
use proc_macro_crate::{crate_name, FoundCrate};

let hal = proc_macro2::Ident::new(
let hal = Ident::new(
if let Ok(FoundCrate::Name(ref name)) = crate_name("esp-hal") {
name
} else {
Expand Down Expand Up @@ -240,18 +238,9 @@ pub fn ram(args: TokenStream, input: TokenStream) -> TokenStream {
/// esp_hal::interrupt::Priority::Priority2)]`.
///
/// If no priority is given, `Priority::min()` is assumed
#[cfg(feature = "interrupt")]
#[proc_macro_error2::proc_macro_error]
#[proc_macro_attribute]
pub fn handler(args: TokenStream, input: TokenStream) -> TokenStream {
use darling::{ast::NestedMeta, FromMeta};
use proc_macro::Span;
use proc_macro2::Ident;
use proc_macro_crate::{crate_name, FoundCrate};
use syn::{parse::Error as ParseError, spanned::Spanned, ItemFn, ReturnType, Type};

use self::interrupt::{check_attr_whitelist, WhiteListCaller};

#[derive(Debug, FromMeta)]
struct MacroArgs {
priority: Option<syn::Expr>,
Expand Down
4 changes: 3 additions & 1 deletion esp-hal/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -39,9 +39,11 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

### Fixed

- Xtensa devices now correctly enable the `esp-hal-procmacros/rtc-slow` feature (#2594)

### Removed
- Remove more examples. Update doctests. (#2547)

- Remove more examples. Update doctests. (#2547)
- The `configure` and `configure_for_async` DMA channel functions has been removed (#2403)
- The DMA channel objects no longer have `tx` and `rx` fields. (#2526)
- `SysTimerAlarms` has been removed, alarms are now part of the `SystemTimer` struct (#2576)
Expand Down
12 changes: 6 additions & 6 deletions esp-hal/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ log = { version = "0.4.22", optional = true }
nb = "1.1.0"
paste = "1.0.15"
portable-atomic = { version = "1.9.0", default-features = false }
procmacros = { version = "0.15.0", features = ["enum-dispatch", "interrupt", "ram"], package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
procmacros = { version = "0.15.0", package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
strum = { version = "0.26.3", default-features = false, features = ["derive"] }
void = { version = "1.0.2", default-features = false }
usb-device = { version = "0.3.2", optional = true }
Expand Down Expand Up @@ -104,19 +104,19 @@ log = ["dep:log"]

# Chip Support Feature Flags
# Target the ESP32.
esp32 = ["dep:esp32", "xtensa-lx-rt/esp32"]
esp32 = ["dep:esp32", "procmacros/rtc-slow", "xtensa-lx-rt/esp32"]
# Target the ESP32-C2.
esp32c2 = ["dep:esp32c2", "portable-atomic/unsafe-assume-single-core"]
# Target the ESP32-C3.
esp32c3 = ["dep:esp32c3", "portable-atomic/unsafe-assume-single-core", "esp-riscv-rt/rtc-ram"]
esp32c3 = ["dep:esp32c3", "esp-riscv-rt/rtc-ram", "portable-atomic/unsafe-assume-single-core"]
# Target the ESP32-C6.
esp32c6 = ["dep:esp32c6", "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
esp32c6 = ["dep:esp32c6", "esp-riscv-rt/rtc-ram", "procmacros/has-lp-core"]
# Target the ESP32-H2.
esp32h2 = ["dep:esp32h2", "esp-riscv-rt/rtc-ram"]
# Target the ESP32-S2.
esp32s2 = ["dep:esp32s2", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
esp32s2 = ["dep:esp32s2", "portable-atomic/critical-section", "procmacros/has-ulp-core", "procmacros/rtc-slow", "usb-otg", "xtensa-lx-rt/esp32s2"]
# Target the ESP32-S3.
esp32s3 = ["dep:esp32s3", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s3", "usb-otg"]
esp32s3 = ["dep:esp32s3", "procmacros/has-ulp-core", "procmacros/rtc-slow", "usb-otg", "xtensa-lx-rt/esp32s3"]

#! ### RISC-V Exclusive Feature Flags
## Move the stack to start of RAM to get zero-cost stack overflow protection
Expand Down