GitHub - eslamHegazy/Assignment1: Designing a counter to count from 0 to 59 using VHDL to be installed on Altera DE10-Lite

eslamHegazy / Assignment1 Public

Designing a counter to count from 0 to 59 using VHDL to be installed on Altera DE10-Lite

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
Assignment1.qpf		Assignment1.qpf
Assignment1.qsf		Assignment1.qsf
Assignment1.qws		Assignment1.qws
Assignment1.vhd		Assignment1.vhd
Assignment1.vhd.bak		Assignment1.vhd.bak
Assignment1_nativelink_simulation.rpt		Assignment1_nativelink_simulation.rpt
bcd.vhd		bcd.vhd
bcd.vhd.bak		bcd.vhd.bak
counter.vhd		counter.vhd
freq_div.vhdl		freq_div.vhdl