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Add broadcast mode to DMA #425

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Add broadcast mode to DMA #425

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3a64725
external dma slots + interfaced fifo example
Oct 19, 2023
f802d4a
typo + copyright update + DMA driver symbols
Oct 19, 2023
2d74f5a
Merge branch 'esl-epfl:main' into main
grinningmosfet Oct 19, 2023
4e0265f
better warning in iffifo_gen.sh
Oct 19, 2023
80230dc
Merge branch 'main' of https://github.com/grinningmosfet/x-heep into …
Oct 19, 2023
a28b550
replace window interface by registers
Oct 20, 2023
e2ada1a
revert i2s, swap 0/1 by TX/RX, iffifo fifo instance typo
Oct 23, 2023
ad9da35
typo
Oct 23, 2023
895153c
swap fifo, adapt example
Oct 24, 2023
9678953
improve interrupts handling
Oct 24, 2023
906362e
status register + interrupts
Oct 25, 2023
192f13e
Merge branch 'esl-epfl:main' into main
grinningmosfet Oct 25, 2023
f15c86a
fix interrupts
Oct 28, 2023
22d02a4
typo
Oct 28, 2023
c79cba0
typos
Oct 28, 2023
eaa058e
merge examples
Oct 28, 2023
a6bb239
implement broadcast dma mode + typos
Oct 31, 2023
b93aa45
implement broadcast dma mode
Oct 31, 2023
f3e91f1
add broadcast destination pointer, increment and slots registers
Oct 31, 2023
9164cb8
add dma broadcast example
Oct 31, 2023
cc3579f
broadcast mode implementation
Nov 1, 2023
96e6f6d
Merge branch 'esl-epfl:main' into main
grinningmosfet Nov 1, 2023
2a8ed5d
Merge branch 'esl-epfl:main' into dma-broadcast
grinningmosfet Nov 1, 2023
7e001cd
Merge branch 'esl-epfl:main' into main
grinningmosfet Nov 20, 2023
998bb84
Merge branch 'esl-epfl:main' into dma-broadcast
grinningmosfet Nov 20, 2023
70c6e84
minor changes
Nov 20, 2023
a2d367d
fix dma indent
Nov 20, 2023
c6eebeb
minor changes
Nov 20, 2023
852292e
verible
Nov 20, 2023
74c16f9
typo
Nov 21, 2023
4cc540b
minor changes
Nov 22, 2023
24a09e1
typo
Nov 22, 2023
ab39ff5
Merge branch 'esl-epfl:main' into main
grinningmosfet Nov 22, 2023
6ba74ec
Merge pull request #2 from grinningmosfet/main
grinningmosfet Nov 22, 2023
64a5dc1
add non-word DU and broadcast tests
Nov 22, 2023
c0e687d
clean example
Nov 22, 2023
c3e8751
Merge branch 'esl-epfl:main' into dma-broadcast
grinningmosfet Nov 29, 2023
3b20b8e
code review: dma refactor
Nov 29, 2023
1ff00cc
minoor fixes
Nov 29, 2023
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8 changes: 4 additions & 4 deletions hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -82,8 +82,8 @@ module ao_peripheral_subsystem
input obi_resp_t dma_read_ch0_resp_i,
output obi_req_t dma_write_ch0_req_o,
input obi_resp_t dma_write_ch0_resp_i,
output obi_req_t dma_addr_ch0_req_o,
input obi_resp_t dma_addr_ch0_resp_i,
output obi_req_t dma_addr_bcst_ch0_req_o,
input obi_resp_t dma_addr_bcst_ch0_resp_i,
output logic dma_done_intr_o,
output logic dma_window_intr_o,

Expand Down Expand Up @@ -392,8 +392,8 @@ module ao_peripheral_subsystem
.dma_read_ch0_resp_i,
.dma_write_ch0_req_o,
.dma_write_ch0_resp_i,
.dma_addr_ch0_req_o,
.dma_addr_ch0_resp_i,
.dma_addr_bcst_ch0_req_o,
.dma_addr_bcst_ch0_resp_i,
.trigger_slot_i(dma_trigger_slots),
.dma_done_intr_o(dma_done_intr_o),
.dma_window_intr_o(dma_window_intr_o)
Expand Down
20 changes: 10 additions & 10 deletions hw/core-v-mini-mcu/core_v_mini_mcu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -294,8 +294,8 @@ module core_v_mini_mcu
input obi_resp_t ext_dma_read_ch0_resp_i,
output obi_req_t ext_dma_write_ch0_req_o,
input obi_resp_t ext_dma_write_ch0_resp_i,
output obi_req_t ext_dma_addr_ch0_req_o,
input obi_resp_t ext_dma_addr_ch0_resp_i,
output obi_req_t ext_dma_addr_bcst_ch0_req_o,
input obi_resp_t ext_dma_addr_bcst_ch0_resp_i,

output reg_req_t ext_peripheral_slave_req_o,
input reg_rsp_t ext_peripheral_slave_resp_i,
Expand Down Expand Up @@ -349,8 +349,8 @@ module core_v_mini_mcu
obi_resp_t dma_read_ch0_resp;
obi_req_t dma_write_ch0_req;
obi_resp_t dma_write_ch0_resp;
obi_req_t dma_addr_ch0_req;
obi_resp_t dma_addr_ch0_resp;
obi_req_t dma_addr_bcst_ch0_req;
obi_resp_t dma_addr_bcst_ch0_resp;

// ram signals
obi_req_t [core_v_mini_mcu_pkg::NUM_BANKS-1:0] ram_slave_req;
Expand Down Expand Up @@ -510,8 +510,8 @@ module core_v_mini_mcu
.dma_read_ch0_resp_o(dma_read_ch0_resp),
.dma_write_ch0_req_i(dma_write_ch0_req),
.dma_write_ch0_resp_o(dma_write_ch0_resp),
.dma_addr_ch0_req_i(dma_addr_ch0_req),
.dma_addr_ch0_resp_o(dma_addr_ch0_resp),
.dma_addr_bcst_ch0_req_i(dma_addr_bcst_ch0_req),
.dma_addr_bcst_ch0_resp_o(dma_addr_bcst_ch0_resp),
.ext_xbar_master_req_i(ext_xbar_master_req_i),
.ext_xbar_master_resp_o(ext_xbar_master_resp_o),
.ram_req_o(ram_slave_req),
Expand All @@ -534,8 +534,8 @@ module core_v_mini_mcu
.ext_dma_read_ch0_resp_i(ext_dma_read_ch0_resp_i),
.ext_dma_write_ch0_req_o(ext_dma_write_ch0_req_o),
.ext_dma_write_ch0_resp_i(ext_dma_write_ch0_resp_i),
.ext_dma_addr_ch0_req_o(ext_dma_addr_ch0_req_o),
.ext_dma_addr_ch0_resp_i(ext_dma_addr_ch0_resp_i)
.ext_dma_addr_bcst_ch0_req_o(ext_dma_addr_bcst_ch0_req_o),
.ext_dma_addr_bcst_ch0_resp_i(ext_dma_addr_bcst_ch0_resp_i)
);

memory_subsystem #(
Expand Down Expand Up @@ -605,8 +605,8 @@ module core_v_mini_mcu
.dma_read_ch0_resp_i(dma_read_ch0_resp),
.dma_write_ch0_req_o(dma_write_ch0_req),
.dma_write_ch0_resp_i(dma_write_ch0_resp),
.dma_addr_ch0_req_o(dma_addr_ch0_req),
.dma_addr_ch0_resp_i(dma_addr_ch0_resp),
.dma_addr_bcst_ch0_req_o(dma_addr_bcst_ch0_req),
.dma_addr_bcst_ch0_resp_i(dma_addr_bcst_ch0_resp),
.dma_done_intr_o(dma_done_intr),
.dma_window_intr_o(dma_window_intr),
.spi_intr_event_o(spi_intr),
Expand Down
20 changes: 10 additions & 10 deletions hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -48,8 +48,8 @@ ${pad.core_v_mini_mcu_interface}
input obi_resp_t ext_dma_read_ch0_resp_i,
output obi_req_t ext_dma_write_ch0_req_o,
input obi_resp_t ext_dma_write_ch0_resp_i,
output obi_req_t ext_dma_addr_ch0_req_o,
input obi_resp_t ext_dma_addr_ch0_resp_i,
output obi_req_t ext_dma_addr_bcst_ch0_req_o,
input obi_resp_t ext_dma_addr_bcst_ch0_resp_i,

output reg_req_t ext_peripheral_slave_req_o,
input reg_rsp_t ext_peripheral_slave_resp_i,
Expand Down Expand Up @@ -103,8 +103,8 @@ ${pad.core_v_mini_mcu_interface}
obi_resp_t dma_read_ch0_resp;
obi_req_t dma_write_ch0_req;
obi_resp_t dma_write_ch0_resp;
obi_req_t dma_addr_ch0_req;
obi_resp_t dma_addr_ch0_resp;
obi_req_t dma_addr_bcst_ch0_req;
obi_resp_t dma_addr_bcst_ch0_resp;

// ram signals
obi_req_t [core_v_mini_mcu_pkg::NUM_BANKS-1:0] ram_slave_req;
Expand Down Expand Up @@ -264,8 +264,8 @@ ${pad.core_v_mini_mcu_interface}
.dma_read_ch0_resp_o(dma_read_ch0_resp),
.dma_write_ch0_req_i(dma_write_ch0_req),
.dma_write_ch0_resp_o(dma_write_ch0_resp),
.dma_addr_ch0_req_i(dma_addr_ch0_req),
.dma_addr_ch0_resp_o(dma_addr_ch0_resp),
.dma_addr_bcst_ch0_req_i(dma_addr_bcst_ch0_req),
.dma_addr_bcst_ch0_resp_o(dma_addr_bcst_ch0_resp),
.ext_xbar_master_req_i(ext_xbar_master_req_i),
.ext_xbar_master_resp_o(ext_xbar_master_resp_o),
.ram_req_o(ram_slave_req),
Expand All @@ -288,8 +288,8 @@ ${pad.core_v_mini_mcu_interface}
.ext_dma_read_ch0_resp_i(ext_dma_read_ch0_resp_i),
.ext_dma_write_ch0_req_o(ext_dma_write_ch0_req_o),
.ext_dma_write_ch0_resp_i(ext_dma_write_ch0_resp_i),
.ext_dma_addr_ch0_req_o(ext_dma_addr_ch0_req_o),
.ext_dma_addr_ch0_resp_i(ext_dma_addr_ch0_resp_i)
.ext_dma_addr_bcst_ch0_req_o(ext_dma_addr_bcst_ch0_req_o),
.ext_dma_addr_bcst_ch0_resp_i(ext_dma_addr_bcst_ch0_resp_i)
);

memory_subsystem #(
Expand Down Expand Up @@ -357,8 +357,8 @@ ${pad.core_v_mini_mcu_interface}
.dma_read_ch0_resp_i(dma_read_ch0_resp),
.dma_write_ch0_req_o(dma_write_ch0_req),
.dma_write_ch0_resp_i(dma_write_ch0_resp),
.dma_addr_ch0_req_o(dma_addr_ch0_req),
.dma_addr_ch0_resp_i(dma_addr_ch0_resp),
.dma_addr_bcst_ch0_req_o(dma_addr_bcst_ch0_req),
.dma_addr_bcst_ch0_resp_i(dma_addr_bcst_ch0_resp),
.dma_done_intr_o(dma_done_intr),
.dma_window_intr_o(dma_window_intr),
.spi_intr_event_o(spi_intr),
Expand Down
2 changes: 1 addition & 1 deletion hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ package core_v_mini_mcu_pkg;
localparam logic [31:0] DEBUG_MASTER_IDX = 2;
localparam logic [31:0] DMA_READ_CH0_IDX = 3;
localparam logic [31:0] DMA_WRITE_CH0_IDX = 4;
localparam logic [31:0] DMA_ADDR_CH0_IDX = 5;
localparam logic [31:0] DMA_ADDR_BCST_CH0_IDX = 5;

localparam SYSTEM_XBAR_NMASTER = 6;

Expand Down
16 changes: 8 additions & 8 deletions hw/core-v-mini-mcu/system_bus.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@ module system_bus
input obi_req_t dma_write_ch0_req_i,
output obi_resp_t dma_write_ch0_resp_o,

input obi_req_t dma_addr_ch0_req_i,
output obi_resp_t dma_addr_ch0_resp_o,
input obi_req_t dma_addr_bcst_ch0_req_i,
output obi_resp_t dma_addr_bcst_ch0_resp_o,

// External master ports
input obi_req_t [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_req_i,
Expand Down Expand Up @@ -82,8 +82,8 @@ module system_bus
output obi_req_t ext_dma_write_ch0_req_o,
input obi_resp_t ext_dma_write_ch0_resp_i,

output obi_req_t ext_dma_addr_ch0_req_o,
input obi_resp_t ext_dma_addr_ch0_resp_i
output obi_req_t ext_dma_addr_bcst_ch0_req_o,
input obi_resp_t ext_dma_addr_bcst_ch0_resp_i
);

import core_v_mini_mcu_pkg::*;
Expand Down Expand Up @@ -121,7 +121,7 @@ module system_bus
assign int_master_req[core_v_mini_mcu_pkg::DEBUG_MASTER_IDX] = debug_master_req_i;
assign int_master_req[core_v_mini_mcu_pkg::DMA_READ_CH0_IDX] = dma_read_ch0_req_i;
assign int_master_req[core_v_mini_mcu_pkg::DMA_WRITE_CH0_IDX] = dma_write_ch0_req_i;
assign int_master_req[core_v_mini_mcu_pkg::DMA_ADDR_CH0_IDX] = dma_addr_ch0_req_i;
assign int_master_req[core_v_mini_mcu_pkg::DMA_ADDR_BCST_CH0_IDX] = dma_addr_bcst_ch0_req_i;

// Internal + external master requests
generate
Expand All @@ -144,7 +144,7 @@ module system_bus
assign debug_master_resp_o = int_master_resp[core_v_mini_mcu_pkg::DEBUG_MASTER_IDX];
assign dma_read_ch0_resp_o = int_master_resp[core_v_mini_mcu_pkg::DMA_READ_CH0_IDX];
assign dma_write_ch0_resp_o = int_master_resp[core_v_mini_mcu_pkg::DMA_WRITE_CH0_IDX];
assign dma_addr_ch0_resp_o = int_master_resp[core_v_mini_mcu_pkg::DMA_ADDR_CH0_IDX];
assign dma_addr_bcst_ch0_resp_o = int_master_resp[core_v_mini_mcu_pkg::DMA_ADDR_BCST_CH0_IDX];

// External master responses
if (EXT_XBAR_NMASTER == 0) begin
Expand All @@ -171,7 +171,7 @@ module system_bus
assign ext_debug_master_req_o = demux_xbar_req[DEBUG_MASTER_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
assign ext_dma_read_ch0_req_o = demux_xbar_req[DMA_READ_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
assign ext_dma_write_ch0_req_o = demux_xbar_req[DMA_WRITE_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
assign ext_dma_addr_ch0_req_o = demux_xbar_req[DMA_ADDR_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
assign ext_dma_addr_bcst_ch0_req_o = demux_xbar_req[DMA_ADDR_BCST_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];

// Internal slave responses
assign int_slave_resp[core_v_mini_mcu_pkg::ERROR_IDX] = error_slave_resp;
Expand All @@ -189,7 +189,7 @@ module system_bus
assign demux_xbar_resp[DEBUG_MASTER_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_debug_master_resp_i;
assign demux_xbar_resp[DMA_READ_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_read_ch0_resp_i;
assign demux_xbar_resp[DMA_WRITE_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_write_ch0_resp_i;
assign demux_xbar_resp[DMA_ADDR_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_addr_ch0_resp_i;
assign demux_xbar_resp[DMA_ADDR_BCST_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_addr_bcst_ch0_resp_i;

`ifndef SYNTHESIS
always_ff @(posedge clk_i, negedge rst_ni) begin : check_out_of_bound
Expand Down
4 changes: 2 additions & 2 deletions hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
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Expand Up @@ -123,8 +123,8 @@ module xilinx_core_v_mini_mcu_wrapper
.ext_dma_read_ch0_resp_i('0),
.ext_dma_write_ch0_req_o(),
.ext_dma_write_ch0_resp_i('0),
.ext_dma_addr_ch0_req_o(),
.ext_dma_addr_ch0_resp_i('0),
.ext_dma_addr_bcst_ch0_req_o(),
.ext_dma_addr_bcst_ch0_resp_i('0),
.ext_peripheral_slave_req_o(),
.ext_peripheral_slave_resp_i('0),
.external_subsystem_powergate_switch_no(),
Expand Down
28 changes: 25 additions & 3 deletions hw/ip/dma/data/dma.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -25,12 +25,12 @@
{ bits: "31:0", name: "PTR_OUT", desc: "Output data pointer (word aligned)" }
]
},
{ name: "ADDR_PTR",
desc: "Addess data pointer (word aligned)",
{ name: "ADDR_BCST_PTR",
desc: "Addess/Broadcast data pointer (word aligned)",
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "31:0", name: "PTR_ADDR", desc: "Address data pointer (word aligned) - used only in Address mode" }
{ bits: "31:0", name: "PTR_ADDR", desc: "Address/Broadcast data pointer (word aligned) - used only in Address and Broadcast modes" }
]
},
{ name: "SIZE",
Expand Down Expand Up @@ -68,6 +68,11 @@
name: "DST_PTR_INC",
desc: "Destination pointer increment",
resval:4
},
{ bits: "23:16",
name: "BCST_PTR_INC",
desc: "Broadcast pointer increment",
resval:4
}
]
},
Expand All @@ -87,6 +92,22 @@
}
]
},
{ name: "BSLOT",
desc: '''The DMA will wait for the signal
connected to the selected trigger_slots to be high
on the read and write side respectivly''',
swaccess: "rw",
hwaccess: "hro",
resval: 0,
fields: [
{ bits: "15:0", name: "BX_TRIGGER_SLOT",
desc: "Broadcast slot selection mask"
},
{ bits: "31:16", name: "DX_TRIGGER_SLOT",
desc: "Dummy slot selection mask"
}
]
},
{ name: "DATA_TYPE",
desc: '''Width/type of the data to transfer''',
swaccess: "rw",
Expand Down Expand Up @@ -115,6 +136,7 @@
{ value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"},
{ value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"},
{ value: "2", name: "ADDRESS_MODE" , desc: "Transfers data using as destination address the data from ADD_PTR"},
{ value: "3", name: "BROADCAST_MODE" , desc: "Equivalent to LINEAR_MODE but writing at two destinations simultaneously"},
]
}
]
Expand Down
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