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make example_iffifo build
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Marc Bornand committed May 22, 2024
1 parent 5627946 commit 595ba86
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6 changes: 6 additions & 0 deletions .gitignore
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Expand Up @@ -9,6 +9,7 @@ build/
*.do
*.jou
*.str
*.pickle
.venv/
__pycache__/

Expand Down Expand Up @@ -47,6 +48,11 @@ sw/device/lib/drivers/power_manager/power_manager_regs.h
sw/device/lib/drivers/power_manager/power_manager.h
sw/device/lib/drivers/pad_control/pad_control_regs.h
sw/device/lib/drivers/**/*_structs.h
sw/device/lib/drivers/rv_plic/rv_plic_gen.c
sw/device/lib/drivers/rv_plic/rv_plic_gen.h
sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.c
sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.h
sw/device/lib/drivers/dma/dma.h

# openroad
flow/OpenROAD-flow-scripts
Expand Down
65 changes: 39 additions & 26 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,8 @@ X_HEEP_CFG ?= configs/general.hjson
PAD_CFG ?= pad_cfg.hjson
EXT_PAD_CFG ?=

DATA_OBJ_FILE=data_cfg.pickle

# Compiler options are 'gcc' (default) and 'clang'
COMPILER ?= gcc

Expand Down Expand Up @@ -94,6 +96,8 @@ conda: environment.yml
environment.yml: python-requirements.txt
util/python-requirements2conda.sh



## @section Installation

## Generates mcu files core-v-mini-mcu files and build the design with fusesoc
Expand All @@ -102,33 +106,39 @@ environment.yml: python-requirements.txt
## @param MEMORY_BANKS=[2(default) to (16 - MEMORY_BANKS_IL)]
## @param MEMORY_BANKS_IL=[0(default),2,4,8]
mcu-gen:
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/include --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/system_bus.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/system_xbar.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/memory_subsystem.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/ao_peripheral_subsystem.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir tb/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv tb/tb_util.svh.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/pad_ring.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/x_heep_system.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link.ld.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.upf.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/ip/power_manager/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/ip/power_manager/data/power_manager.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/ip/power_manager/data --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/ip/power_manager/data/power_manager.hjson.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --cpu $(CPU) --external_domains $(EXTERNAL_DOMAINS) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/core-v-mini-mcu/generated_if.sv.tpl
$(PYTHON) util/mk_cfg.py -o $(DATA_OBJ_FILE) --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --external_pads $(EXT_PAD_CFG)
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu/include --pkg-sv hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu/ --tpl-sv hw/core-v-mini-mcu/system_bus.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu/ --tpl-sv hw/core-v-mini-mcu/system_xbar.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu/ --tpl-sv hw/core-v-mini-mcu/memory_subsystem.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu/ --tpl-sv hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu/ --tpl-sv hw/core-v-mini-mcu/ao_peripheral_subsystem.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir tb/ --tpl-sv tb/tb_util.svh.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/system/ --tpl-sv hw/system/pad_ring.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu/ --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/system/ --tpl-sv hw/system/x_heep_system.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/runtime --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/drivers/rv_plic/ --header-c sw/device/lib/drivers/rv_plic/rv_plic_gen.h.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/drivers/rv_plic/ --header-c sw/device/lib/drivers/rv_plic/rv_plic_gen.c.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/drivers/fast_intr_ctrl/ --header-c sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.c.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/drivers/fast_intr_ctrl/ --header-c sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.h.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/drivers/dma/ --header-c sw/device/lib/drivers/dma/dma.h.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/linker --linker_script sw/linker/link.ld.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir . --pkg-sv ./core-v-mini-mcu.upf.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/ip/power_manager/rtl --pkg-sv hw/ip/power_manager/data/power_manager.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/ip/power_manager/data --pkg-sv hw/ip/power_manager/data/power_manager.hjson.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/core-v-mini-mcu --pkg-sv hw/core-v-mini-mcu/generated_if.sv.tpl
bash -c "cd hw/ip/power_manager; source power_manager_gen.sh; cd ../../../"
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/drivers/power_manager --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv sw/device/lib/drivers/power_manager/data/power_manager.h.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/data --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/data/pad_control.hjson.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/rtl/pad_control.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/drivers/power_manager --pkg-sv sw/device/lib/drivers/power_manager/data/power_manager.h.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/system/pad_control/data --pkg-sv hw/system/pad_control/data/pad_control.hjson.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/system/pad_control/rtl --pkg-sv hw/system/pad_control/rtl/pad_control.sv.tpl
bash -c "cd hw/system/pad_control; source pad_control_gen.sh; cd ../../../"
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link_flash_exec.ld.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link_flash_load.ld.tpl
$(PYTHON) ./util/structs_periph_gen.py
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/fpga/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/fpga/sram_wrapper.sv.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/fpga/scripts/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/fpga/scripts/generate_sram.tcl.tpl
$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/crt/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv sw/device/lib/crt/crt0.S.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/linker --linker_script sw/linker/link_flash_exec.ld.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/linker --linker_script sw/linker/link_flash_load.ld.tpl
$(PYTHON) ./util/structs_periph_gen.py -i ${DATA_OBJ_FILE}
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/fpga/ --tpl-sv hw/fpga/sram_wrapper.sv.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir hw/fpga/scripts/ --tpl-sv hw/fpga/scripts/generate_sram.tcl.tpl
$(PYTHON) util/mcu_gen.py -i ${DATA_OBJ_FILE} --outdir sw/device/lib/crt/ --tpl-sv sw/device/lib/crt/crt0.S.tpl
$(MAKE) verible

## Display mcu_gen.py help
Expand Down Expand Up @@ -298,6 +308,9 @@ app-clean:
app-restore:
rm -rf sw/build

clean-cfg:
@rm -f ${DATA_OBJ_FILE}

## Removes the HW build folder
clean-sim:
@rm -rf build
Expand All @@ -306,4 +319,4 @@ clean-sim:
clean-app: app-restore

## Removes the CMake build folder and the HW build folder
clean-all: app-restore clean-sim
clean-all: app-restore clean-sim clean-cfg
15 changes: 14 additions & 1 deletion configs/example.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
from x_heep_gen.pads import PadManager
from x_heep_gen.system import XHeep, BusType

from x_heep_gen.peripherals.peripheral_domain import PeripheralDomain
from x_heep_gen.peripherals.peripheral_domain import FixedDomain, PeripheralDomain
from x_heep_gen.peripherals.peripherals import *


Expand All @@ -14,6 +14,19 @@ def config():
system.add_linker_section(LinkerSection.by_size("code", 0, 0x00000C800))
system.add_linker_section(LinkerSection("data", 0x00000C800, None))

ao_domain = FixedDomain("ao_peripheral", address=0x20000000, addr_size=0x00100000)
ao_domain.add_peripheral(FixedPeripheral("soc_ctrl", offset=0x00000000, addr_size=0x00010000))
ao_domain.add_peripheral(FixedPeripheral("bootrom", offset=0x00010000, addr_size=0x00010000))
ao_domain.add_peripheral(FixedPeripheral("spi_flash", offset=0x00020000, addr_size=0x00008000))
ao_domain.add_peripheral(FixedPeripheral("spi_memio", offset=0x00028000, addr_size=0x00008000))
ao_domain.add_peripheral(FixedPeripheral("dma", offset=0x00030000, addr_size=0x00010000))
ao_domain.add_peripheral(FixedPeripheral("power_manager", offset=0x00040000, addr_size=0x00010000))
ao_domain.add_peripheral(FixedPeripheral("rv_timer", suffix="ao", offset=0x00050000, addr_size=0x00010000))
ao_domain.add_peripheral(FixedPeripheral("fast_intr_ctrl", offset=0x00060000, addr_size=0x00010000))
ao_domain.add_peripheral(FixedPeripheral("ext_peripheral", offset=0x00070000, addr_size=0x00010000))
ao_domain.add_peripheral(FixedPeripheral("pad_control", offset=0x00080000, addr_size=0x00010000))
system.add_domain(ao_domain)

on_off_domain = PeripheralDomain("peripheral", address=0x30000000, addr_size=0x00100000)
on_off_domain.add_peripheral(RvTimerPeripheral())
on_off_domain.add_peripheral(SpiHostPeripheral(dma=True, event_is_fast_intr=True))
Expand Down
6 changes: 3 additions & 3 deletions docs/source/Peripherals/DMA.md
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Original file line number Diff line number Diff line change
Expand Up @@ -247,7 +247,7 @@ static uint32_t *spi_flash_fifo_tx = ADDRESS_SPI_FLASH_TX_FIFO;

static dma_target_t tgt2= {
.inc_du = 0,
.trig = DMA_TRIG_SLOT_SPI_FLASH_TX,
.trig = DMA_TRIG_SLOT_SPI_FLASH_DMA_TX,
};

tgt2.ptr = spi_flash_fifo_tx;
Expand All @@ -261,7 +261,7 @@ There is no need to assign a value of transaction size or data type. By default,

The increment needs to be set to zero as the pointer should always be set to the FIFO address.

Because the SPI FLASH transmission FIFO has a line connected to slot number 4 (codified as a `1` in the fourth bit of the `trig` element) to let the DMA know if the FIFO is full, a trigger is set in that position by passing `.trig = DMA_TRIG_SLOT_SPI_FLASH_TX`.
Because the SPI FLASH transmission FIFO has a line connected to slot number 4 (codified as a `1` in the fourth bit of the `trig` element) to let the DMA know if the FIFO is full, a trigger is set in that position by passing `.trig = DMA_TRIG_SLOT_SPI_FLASH_DMA_TX`.


The transaction is formed by selecting the source and destination targets
Expand Down Expand Up @@ -401,7 +401,7 @@ The source of the data will be a peripheral connected to the SPI, which will be
tgt2.ptr = spi_peripheral_fifo_rx;
tgt2.size_du = 2048;
tgt2.type = DMA_DATA_TYPE_HALF_WORD;
tgt2.trig = DMA_TRIG_SLOT_SPI_RX;
tgt2.trig = DMA_TRIG_SLOT_SPI_HOST_0_RX;
```

The source pointer is set to the reception FIFO of the SPI, and the appropriate slot is chosen.
Expand Down
20 changes: 10 additions & 10 deletions hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -70,10 +70,10 @@ module ao_peripheral_subsystem
output reg_req_t ext_peripheral_slave_req_o,
input reg_rsp_t ext_peripheral_slave_resp_i,

if_bundle__ao_periph__root.ao_periph bundle__ao_periph__root__if,
if_bundle__ao_periph__pd_peripheral.ao_periph bundle__ao_periph__pd_peripheral__if,
if_bundle__ao_periph__pad_ring.ao_periph bundle__ao_periph__pad_ring__if,
if_bundle__ao_periph__core_v_mini_mcu.ao_periph bundle__ao_periph__core_v_mini_mcu__if
if_bundle__ao_periph__root.ao_periph bundle__ao_periph__root__if,
if_bundle__ao_periph__core_v_mini_mcu.ao_periph bundle__ao_periph__core_v_mini_mcu__if,
if_bundle__ao_periph__pad_ring.ao_periph bundle__ao_periph__pad_ring__if
);

import core_v_mini_mcu_pkg::*;
Expand All @@ -83,13 +83,13 @@ module ao_peripheral_subsystem
reg_pkg::reg_req_t peripheral_req;
reg_pkg::reg_rsp_t peripheral_rsp;

reg_pkg::reg_req_t [core_v_mini_mcu_pkg::AO_PERIPHERALS-1:0] ao_peripheral_slv_req;
reg_pkg::reg_rsp_t [core_v_mini_mcu_pkg::AO_PERIPHERALS-1:0] ao_peripheral_slv_rsp;
reg_pkg::reg_req_t [core_v_mini_mcu_pkg::AO_PERIPHERAL_COUNT-1:0] ao_peripheral_slv_req;
reg_pkg::reg_rsp_t [core_v_mini_mcu_pkg::AO_PERIPHERAL_COUNT-1:0] ao_peripheral_slv_rsp;

tlul_pkg::tl_h2d_t rv_timer_tl_h2d;
tlul_pkg::tl_d2h_t rv_timer_tl_d2h;

logic [AO_PERIPHERALS_PORT_SEL_WIDTH-1:0] peripheral_select;
logic [AO_PERIPHERAL_PORT_SEL_WIDTH-1:0] peripheral_select;

logic use_spimemio;

Expand Down Expand Up @@ -155,13 +155,13 @@ module ao_peripheral_subsystem
);

addr_decode #(
.NoIndices(core_v_mini_mcu_pkg::AO_PERIPHERALS),
.NoRules(core_v_mini_mcu_pkg::AO_PERIPHERALS),
.NoIndices(core_v_mini_mcu_pkg::AO_PERIPHERAL_COUNT),
.NoRules(core_v_mini_mcu_pkg::AO_PERIPHERAL_COUNT),
.addr_t(logic [31:0]),
.rule_t(addr_map_rule_pkg::addr_map_rule_t)
) i_addr_decode_soc_regbus_periph_xbar (
.addr_i(peripheral_req.addr),
.addr_map_i(core_v_mini_mcu_pkg::AO_PERIPHERALS_ADDR_RULES),
.addr_map_i(core_v_mini_mcu_pkg::AO_PERIPHERAL_ADDR_RULES),
.idx_o(peripheral_select),
.dec_valid_o(),
.dec_error_o(),
Expand All @@ -170,7 +170,7 @@ module ao_peripheral_subsystem
);

reg_demux #(
.NoPorts(core_v_mini_mcu_pkg::AO_PERIPHERALS),
.NoPorts(core_v_mini_mcu_pkg::AO_PERIPHERAL_COUNT),
.req_t (reg_pkg::reg_req_t),
.rsp_t (reg_pkg::reg_rsp_t)
) reg_demux_i (
Expand Down
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