Fix AWS multi-clock support

esa-tu-darmstadt · Jul 2, 2024 · 0c940a1 · 0c940a1
1 parent 31ca114
commit 0c940a1
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Showing 4 changed files with 38 additions and 20 deletions.
diff --git a/toolflow/vivado/platform/aws/aws.tcl b/toolflow/vivado/platform/aws/aws.tcl
@@ -391,22 +391,22 @@ namespace eval platform {
     # connect_bd_net [tapasco::subsystem::get_port "design" "clk"] [get_bd_pins $ddr_ic/aclk1]
     # connect_bd_net [tapasco::subsystem::get_port "host" "clk"] [get_bd_pins $ddr_ic/aclk]
 
-    set ddr_ic [tapasco::ip::create_axi_ic "ddr_ic" 2 [llength $ddr_available]]
+    set ddr_ic [tapasco::ip::create_axi_sc "ddr_ic" 2 [llength $ddr_available] 2]
+    set_property -dict [list \
+      CONFIG.HAS_ARESETN {1}
+    ] $ddr_ic
+
 
     connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "ACLK"}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S00_* && TYPE == clk}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ M* && TYPE == clk}]
+      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "aclk"}]
 
     connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S01_* && TYPE == clk}]
+      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "aclk1"}]
 
     connect_bd_net [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "ARESETN"}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S00* && TYPE == rst}] \
-      [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ M* && TYPE == rst}]
+      [get_bd_pins -of_objects $ddr_ic -filter {NAME == "aresetn"}]
 
-    connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
+    #connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
       [get_bd_pins -of_objects $ddr_ic -filter {NAME =~ S01_* && TYPE == rst}]
 
     set num_ddr 0
@@ -440,10 +440,13 @@ namespace eval platform {
 
     # connect_bd_intf_net [get_bd_intf_pins "$out_ic/S00_AXI"] [get_bd_intf_pins "$f1_inst/M_AXI_OCL"]
 
-    set out_ic [tapasco::ip::create_axi_ic "out_ic" 1 5]
+    set out_ic [tapasco::ip::create_axi_sc "out_ic" 1 5 2]
+    set_property -dict [list \
+      CONFIG.HAS_ARESETN {1}
+    ] $out_ic
 
     # Without this, Vivado chooses wrong parameters (at least in 2018.3)
-    set_property -dict [list \
+    #set_property -dict [list \
       {CONFIG.ENABLE_ADVANCED_OPTIONS} {1} \
       {CONFIG.XBAR_DATA_WIDTH} {32} \
     ] $out_ic
@@ -455,6 +458,8 @@ namespace eval platform {
     connect_bd_intf_net [get_bd_intf_pins -of_objects $out_ic -filter {NAME == M04_AXI}] $m_mem_gpio
 
     connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
+      [get_bd_pins -of_objects $out_ic -filter {NAME == "aclk"}]
+    #connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
       [get_bd_pins -of_objects $out_ic -filter {NAME == ACLK}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == clk}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == clk}] \
@@ -463,24 +468,29 @@ namespace eval platform {
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M04_* && TYPE == clk}]
 
     connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
+      [get_bd_pins -of_objects $out_ic -filter {NAME == "aclk1"}]
+    #connect_bd_net [tapasco::subsystem::get_port "design" "clk"] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == clk}]
 
     connect_bd_net [tapasco::subsystem::get_port "host" "rst" "peripheral" "resetn"] \
-      [get_bd_pins -of_objects $out_ic -filter {NAME == ARESETN}] \
-      [get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == rst}] \
+      [get_bd_pins -of_objects $out_ic -filter {NAME == "aresetn"}]
+      #[get_bd_pins -of_objects $out_ic -filter {NAME =~ S0* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M01_* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M02_* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M03_* && TYPE == rst}] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M04_* && TYPE == rst}]
 
-    connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
+    #connect_bd_net [tapasco::subsystem::get_port "design" "rst" "peripheral" "resetn"] \
       [get_bd_pins -of_objects $out_ic -filter {NAME =~ M00_* && TYPE == rst}]
 
     connect_bd_intf_net [get_bd_intf_pins -of_objects $f1_inst -filter {NAME == "M_AXI_OCL"}] \
       [get_bd_intf_pins -of_objects $out_ic -filter {NAME == "S00_AXI"}]
 
     # Connect "in" AXI ports
-    set in_ic [tapasco::ip::create_axi_ic "in_ic" 1 1]
+    set in_ic [tapasco::ip::create_axi_sc "in_ic" 1 1]
+    set_property -dict [list \
+      CONFIG.HAS_ARESETN {1}
+    ] $in_ic
 
     connect_bd_net [tapasco::subsystem::get_port "host" "clk"] \
       [get_bd_pins -of_objects $in_ic -filter {TYPE == clk}]

diff --git a/toolflow/vivado/platform/common/plugins/additional_clocks.tcl b/toolflow/vivado/platform/common/plugins/additional_clocks.tcl
@@ -26,6 +26,15 @@
 
 namespace eval additional_clocks {
 
+  proc get_design_clk_wiz {} {
+    set name [::platform::get_platform_name]
+    if {$name == "aws"} {
+      return [get_bd_cells /host/design_clk_wiz]
+    } else {
+      return [get_bd_cells /memory/design_clk_wiz]
+    }
+  }
+
   proc create_clocks {} {
     if {[tapasco::is_feature_enabled "ADDITIONAL_CLOCKS"]} {
       set config [parse_configuration false]
@@ -46,14 +55,13 @@ namespace eval additional_clocks {
       #   set pin [create_bd_pin -type "clk" -dir "O" [lindex $names $i]]
       #   connect_bd_net [get_bd_pins wizard/clk_out$j] $pin
       # }
-      set design_clk_wiz [get_bd_cells /memory/design_clk_wiz]
       for {set i 0} {$i < $num_clocks} {incr i} {
         set j [expr $i + 2]
         set_property -dict [list \
           CONFIG.CLKOUT${j}_USED {true} \
           CONFIG.CLKOUT${j}_REQUESTED_OUT_FREQ [lindex $freqs $i] \
           CONFIG.CLK_OUT${j}_PORT [lindex $names $i] \
-        ] $design_clk_wiz
+        ] [get_design_clk_wiz]
       }
 
       connect_pes $config
@@ -80,7 +88,7 @@ namespace eval additional_clocks {
         foreach pin $pin_list {
           set pin [get_bd_pins $pin]
           disconnect_bd_net [get_bd_nets -of_objects $pin] $pin
-          connect_bd_net [get_bd_pins /memory/design_clk_wiz/$name] $pin
+          connect_bd_net [get_bd_pins [get_design_clk_wiz]/$name] $pin
         }
       }
     }

diff --git a/toolflow/vivado/platform/common/plugins/custom_constraints.tcl b/toolflow/vivado/platform/common/plugins/custom_constraints.tcl
@@ -36,4 +36,4 @@ namespace eval custom_constraints {
   }
 }
 
-tapasco::register_plugin "platform::custom_constraints::parse_constraints_file" "pre-arch"
+tapasco::register_plugin "platform::custom_constraints::parse_constraints_file" "post-arch"
diff --git a/toolflow/vivado/platform/pcie/pcie_base.tcl b/toolflow/vivado/platform/pcie/pcie_base.tcl
@@ -40,7 +40,7 @@
   foreach f [glob -nocomplain -directory "$::env(TAPASCO_HOME_TCL)/platform/${platform_dirname}/plugins" "*.tcl"] {
     source -notrace $f
   }
-
+  
   proc max_masters {} {
     return [list [::tapasco::get_platform_num_slots]]
   }
-Original file line number
+Diff line change
@@ Expand Up / @@ -36,4 +36,4 @@ namespace eval custom_constraints { @@
       }
     }
-    tapasco::register_plugin "platform::custom_constraints::parse_constraints_file" "pre-arch"
+    tapasco::register_plugin "platform::custom_constraints::parse_constraints_file" "post-arch"