connect module to riscv

Makefile

@@ -4,6 +4,7 @@ PYNQ=xc7z020clg400-1
 XLEN?=32
 CACHE?=false
 MAXI?=1
+ADD_MODULE?="false"
 
 ifndef TAPASCO_HOME
 $(error TAPASCO_HOME is not set, make sure to source setup.sh in TaPaSCo dir)
@@ -26,7 +27,7 @@ list:
 	@echo $(CORE_LIST)
 
 %_pe: %_setup
-	vivado -nolog -nojournal -mode batch -source riscv_pe_project.tcl -tclargs --part $(PYNQ) --bram $(BRAM_SIZE) --cache $(CACHE) --maxi $(MAXI) --project_name $@
+	vivado -nolog -nojournal -mode batch -source riscv_pe_project.tcl -tclargs --part $(PYNQ) --bram $(BRAM_SIZE) --cache $(CACHE) --add_module $(ADD_MODULE) --maxi $(MAXI) --project_name $@
 	@PE_ID=$$(($$(echo $(PE_LIST) | sed s/$@.*// | wc -w) + 1742)); \
 	tapasco -v import IP/$@/esa.informatik.tu-darmstadt.de_tapasco_$@_1.0.zip as $$PE_ID --skipEvaluation
 

common/add_module.tcl

@@ -0,0 +1,81 @@
+source common/module_info.tcl
+# read component.xml
+set component $moddir/component.xml
+set rc [open $component r]
+set fi [read $rc]
+close $rc
+set vendorList [lsearch -inline $fi "*spirit:vendor*"]
+set libraryList [lsearch -inline $fi "*spirit:library*"]
+set nameList [lsearch -inline $fi "*spirit:name*"]
+set versionList [lsearch -inline $fi "*spirit:version*"]
+
+set List {$vendorList $libraryList $nameList $versionList}
+set xL {vendor library name version}
+set i 0
+foreach elem $List {
+lassign [lindex [split [lindex [split [subst $elem] "<"] 1] ">"] 1] [lindex $xL $i]
+incr i
+}
+
+set rv_cell [get_bd_cells -filter "VLNV==$current_core"]
+delete_bd_objs [get_bd_intf_nets axi_mem_intercon_1_M00_AXI]
+
+#create modules
+set $name [ create_bd_cell -type ip -vlnv $vendor:$library:$name:$version $name ]
+if {$project_name == "swerv_pe"} {
+	set project_obj swerv_0
+}
+if {$project_name == "orca_pe"} {
+        set project_obj orca_0
+}
+set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+if {${if_type} == "AXI_APB"} {
+	set axi_apb_bridge_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge_0]
+	set_property -dict [list CONFIG.C_M_APB_PROTOCOL {apb4}] [get_bd_cells axi_apb_bridge_0]
+	set_property -dict [list CONFIG.C_APB_NUM_SLAVES {1}] [get_bd_cells axi_apb_bridge_0]
+}
+set_property -dict [list CONFIG.NUM_SI {2}] [get_bd_cells smartconnect_0]
+set_property -dict [list CONFIG.NUM_MI {2}] [get_bd_cells axi_interconnect_0]
+
+#connect intf
+connect_bd_intf_net [get_bd_intf_pins -filter {MODE==Master} -of [get_bd_cells $name]] [get_bd_intf_pins smartconnect_0/S00_AXI]
+connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins dmaOffset/S_AXI]
+if {${if_type} == "AXI_APB"} {
+	connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_apb_bridge_0/APB_M] [get_bd_intf_pins -filter {MODE==Slave} -of [get_bd_cells $name]]
+	connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins axi_apb_bridge_0/AXI4_LITE]
+} 
+if {${if_type} == "AXI4_LITE"} {
+	connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins -filter {MODE==Slave} -of [get_bd_cells $name]]
+}
+
+make_bd_intf_pins_external  [get_bd_intf_pins axi_offset_0/M_AXI]
+connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_mem_intercon_1/M00_AXI] [get_bd_intf_pins smartconnect_0/S01_AXI]
+
+#connect ports
+
+#CLK
+connect_bd_net [get_bd_ports CLK] [get_bd_pins -filter {TYPE=="clk"} -of [get_bd_cells $name]] [get_bd_pins smartconnect_0/aclk] [get_bd_pins axi_interconnect_0/M01_ACLK]
+if {${if_type} == "AXI_APB"} {
+	connect_bd_net [get_bd_ports CLK] [get_bd_pins axi_apb_bridge_0/s_axi_aclk]
+}
+
+#RST
+connect_bd_net [get_bd_pins rst_CLK_100M/peripheral_aresetn] [get_bd_pins -filter {TYPE=="rst"} -of [get_bd_cells $name]] [get_bd_pins axi_interconnect_0/M01_ARESETN]
+if {${if_type} == "AXI_APB"} {
+	connect_bd_net [get_bd_pins rst_CLK_100M/peripheral_aresetn] [get_bd_pins axi_apb_bridge_0/s_axi_aresetn]
+}
+connect_bd_net [get_bd_pins smartconnect_0/aresetn] [get_bd_pins rst_CLK_100M/interconnect_aresetn]
+
+#INTR
+if {${module_has_intr} == "true"} {
+	if {$project_name == "swerv_pe"} {
+		connect_bd_net [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $name]] [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $project_obj]]
+	}
+	if {$project_name == "orca_pe"} {
+		startgroup
+		set_property -dict [list CONFIG.ENABLE_EXCEPTIONS {1} CONFIG.ENABLE_EXT_INTERRUPTS {1}] [get_bd_cells $project_obj]
+                endgroup
+		connect_bd_net [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $name]] [get_bd_pins -filter {TYPE=="intr"} -of [get_bd_cells $project_obj]]
+        }
+
+}

common/common_addr_segments.tcl

@@ -41,6 +41,19 @@ if {$maxi_ports == 2} {
 create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_CTRL] [get_bd_addr_segs AXIGate_0/saxi/reg0] SEG_AXIGate_0_reg0
 create_bd_addr_seg -range $lmem -offset $lmem [get_bd_addr_spaces S_AXI_BRAM] [get_bd_addr_segs ps_dmem_ctrl/S_AXI/Mem0] SEG_ps_dmem_ctrl_Mem0
 create_bd_addr_seg -range $lmem -offset 0x00000000 [get_bd_addr_spaces S_AXI_BRAM] [get_bd_addr_segs ps_imem_ctrl/S_AXI/Mem0] SEG_ps_imem_ctrl_Mem0
+create_specific_addr_segs
 
+if { ${add_module} eq "true" } {
+	assign_bd_address
+	if { ${change_IN} eq "true" } {
+		set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]]
+		set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $project_obj]] *$name*]]
+		set_property range ${in_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]]
+		set_property offset ${in_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells AXIGate_0]] *$name*]]
+	}
+	if { ${change_OUT} eq "true" } {
+		set_property range ${out_if_range} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $name]] *dmaOffset*]]
+        	set_property offset ${out_if_offset} [get_bd_addr_segs [lsearch -inline [get_bd_addr_segs -of [get_bd_cells $name]] *dmaOffset*]]
 
-create_specific_addr_segs
+	}
+}

common/ip_repo_path.tcl

@@ -4,4 +4,5 @@ set_property "ip_repo_paths" "\
 	[file normalize "$origin_dir/IP/axi_offset"] \
 	[file normalize "$origin_dir/IP/axi_ctrl"] \
 	[file normalize "$origin_dir/IP/riscv"] \
+	[file normalize ${moddir}] \
 	" $obj

common/module_info.tcl

@@ -0,0 +1,31 @@
+
+#THIS IS THE INFO FILE FOR THE MODULE YOU WANT TO ADD
+
+
+#directory path to the module
+set moddir ""
+
+#input interface information
+#supported IF Types: "AXI_APB" "AXI4_LITE"
+set change_IN "false"
+set if_type ""
+set in_if_range ""
+set in_if_offset ""
+
+#output interface information
+set change_OUT "false"
+set out_if_range ""
+set out_if_offset ""
+
+#registers
+#has your module an intr? true/false
+set module_has_intr "false"
+
+
+
+
+
+
+
+
+

common/parse_args.tcl

@@ -34,7 +34,8 @@ if { $::argc > 0 } {
       "--part"         { incr i; set part [lindex $::argv $i] }
       "--bram"         { incr i; set lmem [lindex $::argv $i] }
       "--maxi"         { incr i; set maxi_ports [lindex $::argv $i] }
-      "--cache"		   { incr i; set cache [lindex $::argv $i] }
+      "--cache"	       { incr i; set cache [lindex $::argv $i] }
+      "--add_module"       { incr i; set add_module [lindex $::argv $i] }
       "--project_name" { incr i; set project_name [lindex $::argv $i] }
       "--help"         { help }
       default {

riscv_pe_project.tcl

@@ -81,6 +81,13 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
 
 # Set IP repository paths
 set obj [get_filesets sources_1]
+variable add_module
+variable moddir
+if { ${add_module} eq "true" } {
+        source common/module_info.tcl
+  }
+puts $add_module
+puts $moddir
 source common/ip_repo_path.tcl
 set ip_paths [get_property "ip_repo_paths" $obj]
 puts $ip_paths
@@ -93,6 +100,8 @@ update_ip_catalog -rebuild
 proc cr_bd_riscv_pe { parentCell lmem } {
   variable project_name
   variable cache
+  variable add_module
+  variable moddir
   variable maxi_ports
   # CHANGE DESIGN NAME HERE
   set design_name ${project_name}
@@ -144,6 +153,11 @@ proc cr_bd_riscv_pe { parentCell lmem } {
 
   source common/connect_common_ports.tcl
 
+  # Connect modules
+
+  if { ${add_module} eq "true" } {	
+  	source common/add_module.tcl
+  }
 
   # Create address segments
   source common/common_addr_segments.tcl