Make some gpu registers atomic to ensure thread-safety in pfifo::worker

src/hw/video/gpu/pcrtc.hpp

@@ -5,6 +5,7 @@
 #pragma once
 
 #include <cstdint>
+#include <atomic>
 #include "nv2a_defs.hpp"
 
 #define NV_PCRTC 0x00600000
@@ -41,8 +42,8 @@ class pcrtc {
 	friend class pmc;
 	machine *const m_machine;
 	struct {
-		uint32_t int_status;
-		uint32_t int_enabled;
+		std::atomic_uint32_t int_status; // accessed from pfifo::worker with pmc::update_irq()
+		std::atomic_uint32_t int_enabled; // accessed from pfifo::worker with pmc::update_irq()
 		uint32_t fb_addr;
 		uint32_t unknown[1];
 	};

src/hw/video/gpu/pfb.hpp

@@ -5,6 +5,7 @@
 #pragma once
 
 #include <cstdint>
+#include <atomic>
 #include "nv2a_defs.hpp"
 
 #define NV_PFB 0x00100000
@@ -41,6 +42,6 @@ class pfb {
 	struct {
 		uint32_t cfg0, cfg1;
 		uint32_t nvm;
-		uint32_t cstatus;
+		std::atomic_uint32_t cstatus; // accessed from pfifo::worker with nv2a::get_dma_obj()
 	};
 };

src/hw/video/gpu/pmc.hpp

@@ -5,6 +5,7 @@
 #pragma once
 
 #include <cstdint>
+#include <atomic>
 #include "nv2a_defs.hpp"
 
 #define NV_PMC 0x00000000
@@ -83,8 +84,8 @@ class pmc {
 	machine *const m_machine;
 	struct {
 		uint32_t endianness;
-		uint32_t int_status;
-		uint32_t int_enabled;
+		std::atomic_uint32_t int_status; // accessed from pfifo::worker with pmc::update_irq()
+		std::atomic_uint32_t int_enabled; // accessed from pfifo::worker with pmc::update_irq()
 		uint32_t engine_enabled;
 	};
 };

src/hw/video/gpu/ptimer.hpp

@@ -5,6 +5,7 @@
 #pragma once
 
 #include <cstdint>
+#include <atomic>
 #include "nv2a_defs.hpp"
 
 #define NV_PTIMER 0x00009000
@@ -64,8 +65,8 @@ class ptimer {
 	// Counter value when it was stopped
 	uint64_t counter_when_stopped;
 	struct {
-		uint32_t int_status;
-		uint32_t int_enabled;
+		std::atomic_uint32_t int_status; // accessed from pfifo::worker with pmc::update_irq()
+		std::atomic_uint32_t int_enabled; // accessed from pfifo::worker with pmc::update_irq()
 		uint32_t multiplier, divider;
 		uint32_t alarm;
 	};