Merge branch 'main' of https://github.com/efabless/caravel_openframe …

…into main
efabless · Dec 9, 2021 · fa374d7 · fa374d7
2 parents 92f1ab7 + ec93c72
commit fa374d7
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
@@ -28,7 +28,7 @@ module simple_por(
  output por_l
 );
 
- wire mid, porb_h;
+ wire mid;
  reg inode;
 
  // This is a behavioral model! Actual circuit is a resitor dumping