declared ports type as wire and update version

efabless · May 20, 2024 · 1b5391d · 1b5391d
1 parent 4598c0e
commit 1b5391d
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Showing 7 changed files with 14 additions and 14 deletions.
diff --git a/EF_UART.yaml b/EF_UART.yaml
@@ -7,8 +7,8 @@ info:
  license: APACHE 2.0
  author: Mohamed Shalan
  email: [email protected]
- version: v1.1.2
- date: 12-5-2024
+ version: v1.1.3
+ date: 20-5-2024
  category: digital
  tags:
  - peripheral

diff --git a/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
@@ -118,8 +118,8 @@ module EF_UART_AHBL #(
  output wire [31:0] HRDATA,
  output wire IRQ
 ,
- input [1-1:0] rx,
- output [1-1:0] tx
+ input wire [1-1:0] rx,
+ output wire [1-1:0] tx
 );
 
  localparam RXDATA_REG_OFFSET = 16'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_UART_AHBL.v b/hdl/rtl/bus_wrappers/EF_UART_AHBL.v
@@ -34,8 +34,8 @@ module EF_UART_AHBL #(
  FAW = 4
 ) (
  `AHBL_SLAVE_PORTS,
- input [1-1:0] rx,
- output [1-1:0] tx
+ input wire [1-1:0] rx,
+ output wire [1-1:0] tx
 );
 
  localparam RXDATA_REG_OFFSET = `AHBL_AW'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v b/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
@@ -101,8 +101,8 @@ module EF_UART_APB #(
  output wire [31:0] PRDATA,
  output wire IRQ
 ,
- input [1-1:0] rx,
- output [1-1:0] tx
+ input wire [1-1:0] rx,
+ output wire [1-1:0] tx
 );
 
  localparam RXDATA_REG_OFFSET = 16'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.v b/hdl/rtl/bus_wrappers/EF_UART_APB.v
@@ -34,8 +34,8 @@ module EF_UART_APB #(
  FAW = 4
 ) (
  `APB_SLAVE_PORTS,
- input [1-1:0] rx,
- output [1-1:0] tx
+ input wire [1-1:0] rx,
+ output wire [1-1:0] tx
 );
 
  localparam RXDATA_REG_OFFSET = `APB_AW'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_UART_WB.pp.v b/hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
@@ -95,8 +95,8 @@ module EF_UART_WB #(
  output reg ack_o,
  input wire we_i,
  output wire IRQ,
- input [1-1:0] rx,
- output [1-1:0] tx
+  input wire [1-1:0] rx,
+  output wire [1-1:0] tx
 );
 
  localparam RXDATA_REG_OFFSET = 16'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_UART_WB.v b/hdl/rtl/bus_wrappers/EF_UART_WB.v
@@ -34,8 +34,8 @@ module EF_UART_WB #(
  FAW = 4
 ) (
  `WB_SLAVE_PORTS,
- input [1-1:0] rx,
- output [1-1:0] tx
+ input wire [1-1:0] rx,
+ output wire [1-1:0] tx
 );
 
  localparam RXDATA_REG_OFFSET = `WB_AW'h0000;