include clock gate sky 130 cell inside ifdef block for fpga implmenta…

…tion
efabless · Sep 17, 2024 · 06376a9 · 06376a9
1 parent 9d79471
commit 06376a9
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Showing 3 changed files with 36 additions and 28 deletions.
diff --git a/EF_UART.yaml b/EF_UART.yaml
@@ -7,8 +7,8 @@ info:
  license: APACHE 2.0
  author: Mohamed Shalan
  email: [email protected]
- version: v1.1.6
- date: 08-07-2024
+ version: v1.1.7
+ date: 16-09-2024
  category: digital
  tags:
  - peripheral

diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v b/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
@@ -69,19 +69,23 @@ module EF_UART_APB #(
  wire clk_g;
  wire clk_gated_en = GCLK_REG[0];
 
- (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
- `ifdef USE_POWER_PINS
- .VPWR(VPWR), 
- .VGND(VGND), 
- .VNB(VGND),
- .VPB(VPWR),
- `endif
- .GCLK(clk_g), 
- .GATE(clk_gated_en), 
- .CLK(PCLK)
- );
-
- wire clk = clk_g;
+ `ifdef FPGA
+ wire clk = PCLK;
+ `else
+ (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+ `ifdef USE_POWER_PINS 
+ .VPWR(VPWR), 
+ .VGND(VGND), 
+ .VNB(VGND),
+ .VPB(VPWR),
+ `endif
+ .GCLK(clk_g), 
+ .GATE(clk_gated_en), 
+ .CLK(PCLK)
+ );
+
+ wire clk = clk_g;
+ `endif
  wire rst_n = PRESETn;
 
 

diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.v b/hdl/rtl/bus_wrappers/EF_UART_APB.v
@@ -63,19 +63,23 @@ module EF_UART_APB #(
  wire clk_g;
  wire clk_gated_en = GCLK_REG[0];
 
- (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
- `ifdef USE_POWER_PINS 
- .VPWR(VPWR), 
- .VGND(VGND), 
- .VNB(VGND),
- .VPB(VPWR),
- `endif 
- .GCLK(clk_g), 
- .GATE(clk_gated_en), 
- .CLK(PCLK)
- );
-
- wire clk = clk_g;
+ `ifdef FPGA
+ wire clk = PCLK;
+ `else
+ (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+ `ifdef USE_POWER_PINS 
+ .VPWR(VPWR), 
+ .VGND(VGND), 
+ .VNB(VGND),
+ .VPB(VPWR),
+ `endif
+ .GCLK(clk_g), 
+ .GATE(clk_gated_en), 
+ .CLK(PCLK)
+ );
+
+ wire clk = clk_g;
+ `endif
  wire rst_n = PRESETn;