Skip to content
View dineshannayya's full-sized avatar

Block or report dineshannayya

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. riscduino riscduino Public

    Arduino compatible Risc-V Based SOC

    Tcl 139 23

  2. yifive_r0 yifive_r0 Public

    A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program

    Verilog 17 4

  3. usb1_host usb1_host Public

    USB1.1 Host Controller + PHY

    Verilog 11 4

  4. riscduino_dcore riscduino_dcore Public

    Tcl 10 4

  5. riscduino_qcore riscduino_qcore Public

    Tcl 7 5

  6. logic_bist logic_bist Public

    Verilog 5 2